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PEB 20550
PEF 20550
Detailed Register Description
Semiconductor Group
148
01.96
Table 20
Time Slot Encoding for Control Memory Accesses
4.6.15
Access in demultiplexed
μ
P-interface mode:
Access in multiplexed
μ
P-interface mode:
Reset value: xx
H
Memory Access Data Register (MADR)
read/write
read/write
address: 02
H
address: 04
H
The Memory Access Data Register MADR contains the data to be transferred from or to
a memory location. The meaning and the structure of this data depends on the kind of
memory being accessed.
4.6.16
Access in demultiplexed
μ
P-interface mode:
Access in multiplexed
μ
P-interface mode:
Reset value: xx
H
Synchronous Transfer Data Register (STDA)
read/write
read/write
address: 03
H
address: 06
H
The STDA-register buffers the data transferred over the synchronous transfer channel A.
MTDA7 to MTDA0 hold the bits 7 to 0 of the respective time slot. MTDA7 (MSB) is the
bit transmitted/received first, MTDA0 (LSB) the bit transmitted/received last over the
serial interface.
Control Memory Address
bit U/D
bits MA6..MA3, MA0
bits MA2..MA1
bit U/D
bits MA6..MA3, MA2, MA0
bit MA1
bit U/D
bits MA6..MA0
bit U/D
bits MA6..MA4, MA0
bits MA3..MA1
CFI-mode 0
direction selection
time slot selection
logical CFI-port number
direction selection
time slot selection
logical CFI-port number
direction selection
time slot selection
direction selection
time slot selection
logical CFI-port number
CFI-mode 1
CFI-mode 2
CFI-mode 3
bit 7
MD7
bit 0
MD6
MD5
MD4
MD3
MD2
MD1
MD0
bit 7
MTDA7
bit 0
MTDA0
MTDA6
MTDA5
MTDA4
MTDA3
MTDA2
MTDA1