![](http://datasheet.mmic.net.cn/330000/PEF20550_datasheet_16444055/PEF20550_16.png)
PEB 20550
PEF 20550
Overview
Semiconductor Group
16
01.96
1.3
μ
-Processor Interface
Pin No.
Pin Definitions and Functions
Symbol
Input (I)
Output (O)
I
Function
6
CSE
C
hip
S
elect
EPIC-1
; active low. A "low" on this line
selects all registers (excluding the SACCO-
registers) for read/write operations.
C
hip
S
elect
SACCO
; active low. A "low" on this
line selects the SACCO-registers for read/write
operations.
W
rite, active low, Siemens/Intel bus mode.
When "low", a write operation is indicated.
R
ead/
W
rite, Motorola bus mode.
When "high" a valid
μ
P-access identifies a read
operation, when "low" it identifies a write access.
R
ead, active low, Siemens/Intel bus mode.
When "low" a read operation is indicated.
D
ata
S
trobe, Motorola bus mode.
A rising edge marks the end of a read or write
operation.
A
ddress/
D
ata
B
us; multiplexed bus mode.
Transfers addresses from the
μ
P-system to the
ELIC and data between the
μ
P and the ELIC.
D
ata
B
us; demultiplexed bus mode.
Transfers data between the
μ
P and the ELIC.
When driving data the pins have push pull
characteristic, otherwise they are in the state
high impedance.
A
ddress
L
atch
E
nable
ALE controls the on chip address latch in
multiplexed bus mode. While ALE is "high", the
latch is transparent. The falling edge latches the
current address. During the first read/write access
following reset ALE is evaluated to select the bus
mode.
7
CSS
I
8
WR,
R/W
I
9
RD, DS
I
12
13
14
15
16
17
18
19
10
AD0, D0
AD1, D1
AD2, D2
AD3, D3
AD4, D4
AD5, D5
AD6, D6
AD7, D7
ALE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I