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PEB 20550
PEF 20550
Functional Description
Semiconductor Group
66
01.96
According to the PBC conventions, the control response byte has the following structure:
bit7 … 6:
bit5
bit4
10
1
AREP : 1/0: autorepeating is enabled/disabled
(Read back value of CMDR:AREP)
00
: SACCO FIFO available for data reception
DOV
: inverted status of the bit RSTA:RDO (RFIFO overflow)
1
: fixed value, no functionality.
: response to an I-frame, no further data follows
:
μ
P connected (PBC operates optionally in stand alone mode)
:
:
bit3 … 2:
bit1
bit0
:
:
I-Frame with Data
The address is defined by the value stored in XAD1 (1-byte address) or XAD1 and XAD2
(2-byte address). The control byte is fixed to 10
H
(I-frame, final bit = 1). The data field
contains the XFIFO contents.
Note: The control response byte has to be generated by software.
Data Transfer
Polling of Direct Data
When direct data was loaded (XDD executed) an I-frame is generated as a response to
a RR-poll.
After checking STAR:XFW, blocks of up to 32 bytes may be entered in XFIFO. When
more than 32 bytes are to be transmitted the XPR-interrupt is used to indicate that the
CPU accessible XFIFO-part is free again. A maximum of 64 bytes may be stored before
the actual transmission is started.
A RR-acknowledge (poll bit = 0) causes an ISTA:XPR interrupt, XFIFO is cleared and
STAR:XFW is set.
When the SACCO receives a RR-poll frame and no data was loaded in XFIFO it
generates automatically a RR-response.
bit 7
bit 0
1
0
1
AREP
0
0
DOV
1
flag
address
control byte
data
CRC-word
flag