PM7346 S/UNI-QJET
DATASHEET
PMC-960835
ISSUE 6
SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE
79
Stuff Length
C1(Hex)
18
4F
19
75
20
9D
21
A7
The SPLT block generates a stuff length pattern of 18, 19 or 20 octets
determined by the phase alignment of the start of the G.751 E3 frame and the
start of the E3 PLCP frame. The REF8KI input is provisioned to loop time the
PLCP transmit frame to an externally applied 8 kHz reference.
The Zn, growth octets are set to 00H. The Zn octets may be inserted from an
external device via the path overhead stream input, TPOH.
9.19 TXCP-50 Transmit Cell Processor
The Transmit Cell Processor (TXCP-50) Block integrates circuitry to support ATM
cell payload scrambling, header check sequence (HCS) generation, and
idle/unassigned cell generation.
The TXCP-50 scrambles the cell payload field using the self synchronizing
scrambler with polynomial x
43
+ 1. The header portion of the cells may optionally
also be scrambled. Note that cell payload scrambling may be disabled in the
S/UNI-QJET, though it is required by ITU-T Recommendation I.432. The ATM
Forum DS3 UNI specification requires that cell payloads are scrambled for the
DS3 physical layer interface. However, to ensure backwards compatibility with
older equipment, the payload scrambling may be disabled.
The HCS is generated using the polynomial, x
8
+ x
2
+ x + 1. The coset
polynomial x
6
+ x
4
+ x
2
+ 1 is added (modulo 2) to the calculated HCS octet as
required by the ATM Forum UNI specification, and ITU-T Recommendation I.432.
The resultant octet optionally overwrites the HCS octet in the transmit cell. When
the transmit FIFO is empty, the TXCP-50 inserts idle/unassigned cells. The
idle/unassigned cell header is fully programmable using five internal registers.
Similarly, the 48 octet information field is programmed with an 8 bit repeating
pattern using an internal register.