
PM7346 S/UNI-QJET
DATASHEET
PMC-960835
ISSUE 6
SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE
365
register is set to logic 1, as in Figure 70. TGAPCLK remains high during the
overhead bit positions. TDATI is sampled on the falling edge of TGAPCLK.
Figure 71
- Framer Mode G.832 E3 Receive Output Stream
RDATO[x]
Oct 5308
RFPO/RMFPO[x]
Oct 12
Oct 11
FA28
FA11
FA14
FA13
FA12
FA15
FA16
FA17
FA18
Oct 5303
Oct 5301
Oct 5302
Oct 5304
Oct 5305
Oct 5306
Oct 5307
ROVRHD[x]
RSCLK[x]
Figure 72
RGAPCLK
- Framer Mode G.832 E3 Receive Output Stream with
RGAPCLK[x]
RDATO[x]
Oct 5308
Oct 12
Oct 11
Oct 5303
Oct 5301
Oct 5302
Oct 5304
Oct 5305
Oct 5306
Oct 5307
The Framer Mode G.832 E3 Receive Output Stream diagrams (Figure 71 and
Figure 72) show the format of the outputs RDATO, RFPO/RMFPO, RSCLK (and
RGAPCLK), and ROVRHD when the FRMRONLY bit in the S/UNI-QJET
Configuration 1 register is set. Figure 71 shows the data streams when the
S/UNI-QJET is configured for the E3 G.832 receive format. RFPO or RMFPO
pulses high for one RSCLK cycle and is aligned to the first bit of the FA1 byte in
the G.832 E3 output data stream on RDATO. ROVRHD will be high for every
overhead bit position on the RDATO data stream. The RGAPCLK output is
available in place of RSCLK when the RXGAPEN bit in the S/UNI-QJET
Configuration 2 register is set to logic 1. RGAPCLK remains high during the
overhead bit positions as shown in Figure 72.
Figure 73
- Framer Mode J2 Transmit Input Stream
TDATI[x]
TFPI/TMFPI[x]
1
0
1
TS988
x1
x2
x3
e1
TFPO/TMFPO[x]
TS988
TS987
TS986
TS988
TS987
TS986
TSN6
TSN7
TSN8
TICLK[x]