
PM7346 S/UNI-QJET
DATASHEET
PMC-960835
ISSUE 6
SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE
113
Register 00AH, 10AH, 20AH, 30AH: SPLR Interrupt Status
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
R
FEBEI
X
Bit 5
R
COLSSI
X
Bit 4
R
BIPEI
X
Bit 3
R
FEI
X
Bit 2
R
YELI
X
Bit 1
R
LOFI
X
Bit 0
R
OOFI
X
OOFI:
The OOFI bit is set to logic 1 when a PLCP out of frame defect is detected or
removed. The OOF defect state is contained in the SPLR Status Register.
The OOFI bit position is set to logic 0 when this register is read.
LOFI:
The LOFI bit is set to logic 1 when a PLCP loss of frame defect is detected or
removed. The LOF defect state is contained in the SPLR Status Register.
The LOFI bit position is set to logic 0 when this register is read.
YELI:
The YELI bit is set to logic 1 when a PLCP yellow alarm defect is detected or
removed. The yellow alarm defect state is contained in the SPLR Status
Register. The YELI bit position is set to logic 0 when this register is read.
FEI:
The FEI bit is set to logic 1 when a PLCP framing octet error is detected. A
framing octet error is generated when one or more errors are detected in the
framing alignment octets (A1, and A2), or the path overhead identification
octets. The FEI bit position is set to logic 0 when this register is read.
BIPEI:
The BIPEI bit is set to logic 1 when a PLCP bit interleaved parity (BIP) error is
detected. BIP errors are detected using the B1 byte in the PLCP path
overhead. The BIPEI bit position is set to logic 0 when this register is read.