
PM7346 S/UNI-QJET
DATASHEET
PMC-960835
ISSUE 6
SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE
202
Register 052H, 152H, 252H, 352H: RDLC Status
Bit
Type
Function
Default
Bit 7
R
FE
X
Bit 6
R
OVR
X
Bit 5
R
COLS
X
Bit 4
R
PKIN
X
Bit 3
R
PBS[2]
X
Bit 2
R
PBS[1]
X
Bit 1
R
PBS[0]
X
Bit 0
R
INTR
X
Consecutive reads of the RDLC Status and Data registers should not occur at
rates greater than 1/10 that of the clock selected by the LINESYSCLK bit of the
S/UNI-QJET Misc. register (09BH, 19BH, 29BH, 39BH).
INTR:
The interrupt (INTR) bit reflects the status of the internal RDLC interrupt. If
the INTE bit in the RDLC Interrupt Control Register is set to logic 1, a RDLC
interrupt (INTR is a logic 1) will cause INTB to be asserted low. The INTR
register bit will be set to logic 1 when one of the following conditions occurs:
1. the number of bytes specified in the RDLC Interrupt Control register have
been received on the data link and written into the FIFO
2. RDLC FIFO buffer overrun has been detected
3. the last byte of a packet has been written into the RDLC FIFO
4. the last byte of an aborted packet has been written into the RDLC FIFO
5. transition of receiving all ones to receiving flags has been detected.
PBS[2:0]:
The packet byte status (PBS[2:0]) bits indicate the status of the data last read
from the FIFO as indicated in the following table: