
PM7346 S/UNI-QJET
DATASHEET
PMC-960835
ISSUE 6
SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE
311
TOHFP[x], and TOHCLK[x] signals. In the receive direction, most of the
overhead bits our brought out serially on the ROH[x] data stream.
Table 33
- DS3 Frame Overhead Operation
Control Bit
Xx:
X-Bit Channel
Transmit Operation
Inserts the FERF signal on
the X-bits.
Receive Operation
Monitors and detects changes in
the state of the FERF signal on the
X-bits.
Calculates the parity for the
received payload. Errors are
accumulated in internal registers.
Px:
P-Bit Channel
Calculates the parity for the
payload data over the
previous M-frame and inserts
it into the P1 and P2 bit
positions.
Generates the M-frame
alignment signal (M1=0,
M2=1, M3=0).
Mx:
M-Frame
Alignment
Signal
Finds the M-frame alignment by
searching for the F-bits and the M-
bits. Out-of-frame is removed if the
M-bits are correct for three
consecutive M-frames while no
discrepancies have occurred in the
F-bits.
Finds M-frame alignment by
searching for the F-bits and the M-
bits. Out-of-frame is removed if the
M-bits are correct for three
consecutive M-frames while no
discrepancies have occurred in the
F-bits.
The state of the C-bit parity ID bit
is stored in a register. This bit
indicates whether an M23 or C-bit
parity format is received.
Fx:
M-subframe
Alignment
Signal
Generates the M-subframe
signal (F1=1, F2=0, F3=0,
F4=1).
Cx:
C-Bit Channels
M23 Operation:
The C bits are passed
through transparently in M23
framer only mode except for
the C-bit Parity ID bit which
toggles every M-frame. In
M23 ATM applications, the C
bits other than the Parity ID
bit are forced to logic 1.
C-bit Parity Operation:
The C-bit Parity ID bit is
forced to logic 1. The second
C-bit in M-subframe 1 is set
to logic 1. The third C-bit in
M-subframe 1 provides a far-
C-bit Parity Operation:
The FEAC channel on the third C-
bit in M-subframe 1 is detected by
the RBOC block. Path parity errors
and FEBEs on the C-bits in M-
subframes 3 and 4 are
accumulated in counters. The path
maintenance datalink signal is
extracted by the receive HDLC
controller.