
PM7346 S/UNI-QJET
DATASHEET
PMC-960835
ISSUE 6
SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE
222
Register 062H, 162H, 262H, 362H: RXCP-50 FIFO/UTOPIA Control & Config
Bit
Type
Function
Default
Bit 7
R/W
RXPTYP
0
Bit 6
Unused
X
Bit 5
R/W
RCAINV
0
Bit 4
R/W
RCALEVEL0
1
Bit 3
Unused
X
Bit 2
Unused
X
Bit 1
Unused
X
Bit 0
R/W
FIFORST
0
FIFORST:
The FIFORST bit is used to reset the four-cell receive FIFO. When FIFORST
is set to logic 0, the FIFO operates normally. When FIFORST is set to logic 1,
the FIFO is immediately emptied and further writes into the FIFO are ignored
(no incoming ATM cells will be stored in the FIFO). The FIFO remains empty
and continues to ignore writes until a logic 0 is written to FIFORST.
See section 12.8 on resetting the receive and transmit FIFOs.
RCALEVEL0:
The RCALEVEL0 register bit selects the behavior of RCA and DRCA[x] when
they de-assert (transition to logic 0 if RCAINV is logic 0, or transition to logic 1
if RCAINV is logic 1) as the receive FIFO empties.
When RCALEVEL0 is set to logic 1, DRCA[x] and RCA indicates that the
receive FIFO is empty. RCA (and DRCA[x]), if polled, will de-assert on the
rising RFCLK edge after Payload byte 48 (ATM8=1) or Payload byte 24
(ATM8=0) is output.
When RCALEVEL0 is set to logic 0, DRCA[x] and RCA, if polled, indicates
that the receive FIFO is near empty. DRCA[x] and RCA, if polled, will de-
assert on the rising RFCLK edge after Payload byte 43 (ATM8=1) or Payload
byte 19 (ATM8=0) is output.