
PM7346 S/UNI-QJET
DATASHEET
PMC-960835
ISSUE 6
SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE
331
Figure 25
- Example Multi-Packet Operational Sequence
DATA
INT
FE
LA
1
2
3
4 5
6
7
F
F
F
F
A
D
D
D
D
D
D
D
D
D
D D D DD
F
F
F
F
D
D
D
D
FF
F
- flag sequence (01111110)
A
- abort sequence (01111111)
D
- packet data bytes
INT
- active high interrupt output
FE
- internal FIFO empty status
LA
- state of the LINK ACTIVE software flag
Figure 25 shows the timing of interrupts, the state of the FIFO, and the state of
the Data Link relative the input data sequence. The cause of each interrupt and
the processing required at each point is described in the following paragraphs.
At points 1 and 5 the first flag after all ones or abort is detected. A dummy byte
is written in the FIFO, FE goes low, and an interrupt goes high. When the
interrupt is detected by the processor it reads the dummy byte, the FIFO
becomes empty, and the interrupt is removed. The LINK ACTIVE (LA) software
flag is set to logic 1.
At points 2 and 6 the last byte of a packet is detected and interrupt goes high.
When the interrupt is detected by the processor, it reads the data and status
registers until the FIFO becomes empty. The interrupt is removed as soon as the
RDLC Status register is read since the FIFO fill level of 8 bytes has not been
exceeded. It is possible to store many packets in the FIFO and empty the FIFO
when the FIFO fill level is exceeded. In either case the processor should use this
interrupt to count the number of packets written into the FIFO. The packet count
or a software time-out can be used as a signal to empty the FIFO.