
PM7346 S/UNI-QJET
DATASHEET
PMC-960835
ISSUE 6
SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE
147
Register 030H, 130H, 230H, 330H: DS3 FRMR Configuration
Bit
Type
Function
Default
Bit 7
R/W
AISPAT
1
Bit 6
R/W
FDET
0
Bit 5
R/W
MBDIS
0
Bit 4
R/W
M3O8
0
Bit 3
R/W
UNI
0
Bit 2
R/W
REFR
0
Bit 1
R/W
AISC
0
Bit 0
R/W
CBE
0
CBE:
The CBE bit enables the DS3 C-bit parity application. When a logic 1 is
written to CBE, C-bit parity mode is enabled. When a logic 0 is written to
CBE, the DS3 M23 format is selected. While the C-bit parity application is
enabled, C-bit parity error events, far end block errors are accumulated.
AISC:
The AISC bit controls the algorithm used to detect the alarm indication signal
(AIS). When a logic 1 is written to AISC, the algorithm checks that a framed
DS3 signal with all C-bits set to logic 0 is observed for a period of time before
declaring AIS. The payload contents are checked to the pattern selected by
the AISPAT bit. When a logic 0 is written to AISC, the AIS detection algorithm
is determined solely by the settings of AISPAT and AISONES register bits
(see bit mapping table in the Additional Configuration Register description).
REFR:
The REFR bit initiates a DS3 reframe. When a logic 1 is written to REFR, the
S/UNI-QJET is forced out-of-frame, and a new search for frame alignment is
initiated. Note that only a low to high transition of the REFR bit triggers
reframing; multiple write operations are required to ensure such a transition.
UNI:
The UNI bit configures the S/UNI-QJET to accept either dual-rail or single-rail
receive DS3 streams. When a logic 1 is written to UNI, the S/UNI-QJET
accepts a single-rail DS3 stream on RDATI. The S/UNI-QJET accumulates