参数资料
型号: RFPIC12F675K-E/SS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDSO20
封装: 0.209 INCH, PLASTIC, MO-150, SSOP-20
文件页数: 14/123页
文件大小: 5438K
代理商: RFPIC12F675K-E/SS
rfPIC12F675
DS70091A-page 108
Preliminary
2003 Microchip Technology Inc.
FIGURE 13-11:
rfPIC12F675 A/D CONVERSION TIMING (SLEEP MODE)
TABLE 13-10: rfPIC12F675 A/D CONVERSION REQUIREMENTS (SLEEP MODE)
Param
No.
Sym
Characteristic
Min
Typ
Max
Units
Conditions
130
T
AD
A/D Clock Period
1.6
s VREF ≥ 3.0V
3.0*
s VREF full range
130
TAD
A/D Internal RC
Oscillator Period
3.0*
6.0
9.0*
s
ADCS<1:0> = 11 (RC mode)
At V
DD = 2.5V
2.0*
4.0
6.0*
s At VDD = 5.0V
131
T
CNV
Conversion Time
(not including
Acquisition Time)(1)
11
T
AD
132
T
ACQ
Acquisition Time
(Note 2)
5*
11.5
s
s The minimum time is the amplifier
settling time. This may be used if
the “new” input voltage has not
changed by more than 1 LSb (i.e.,
4.1 mV @ 4.096V) from the last
sampled voltage (as stored on
C
HOLD).
134
T
GO
Q4 to A/D Clock
Start
T
OSC/2 + TCY
If the A/D clock source is selected
as RC, a time of T
CY is added
before the A/D clock starts. This
allows the SLEEP instruction to be
executed.
*
These parameters are characterized but not tested.
Data in ‘Typ’ column is at 5.0V, 25
°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: ADRES register may be read on the following T
CY cycle.
2: See Section 7.1 for minimum conditions.
131
130
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
9
7
32
10
Note 1: If the A/D clock source is selected as RC, a time of T
CY is added before the A/D clock starts. This allows the
SLEEP
instruction to be executed.
134
6
8
132
1 T
CY
(T
OSC/2 + TCY)(1)
1 T
CY
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