参数资料
型号: RFPIC12F675K-E/SS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDSO20
封装: 0.209 INCH, PLASTIC, MO-150, SSOP-20
文件页数: 49/123页
文件大小: 5438K
代理商: RFPIC12F675K-E/SS
2003 Microchip Technology Inc.
Preliminary
DS70091A-page 29
rfPIC12F675
5.1
Timer1 Modes of Operation
Timer1 can operate in one of three modes:
16-bit timer with prescaler
16-bit synchronous counter
16-bit asynchronous counter
In Timer mode, Timer1 is incremented on every
instruction
cycle.
In
Counter
mode,
Timer1
is
incremented on the rising edge of the external clock
input T1CKI. In addition, the Counter mode clock can
be synchronized to the microcontroller system clock
or run asynchronously.
In Counter and Timer modules, the counter/timer clock
can be gated by the T1G input.
If an external clock oscillator is needed (and the
microcontroller is using the INTOSC w/o CLKOUT),
Timer1 can use the LP oscillator as a clock source.
5.2
Timer1 Interrupt
The Timer1 register pair (TMR1H:TMR1L) increments
to FFFFh and rolls over to 0000h. When Timer1 rolls
over, the Timer1 interrupt flag bit (PIR1<0>) is set. To
enable the interrupt on rollover, you must set these bits:
Timer1 interrupt Enable bit (PIE1<0>)
PEIE bit (INTCON<6>)
GIE bit (INTCON<7>).
The interrupt is cleared by clearing the TMR1IF in the
Interrupt Service Routine.
5.3
Timer1 Prescaler
Timer1 has four prescaler options allowing 1, 2, 4, or 8
divisions of the clock input. The T1CKPS bits
(T1CON<5:4>) control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write
to TMR1H or TMR1L.
FIGURE 5-2:
TIMER1 INCREMENTING EDGE
Note:
In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge.
Note:
The TMR1H:TTMR1L register pair and the
TMR1IF bit should be cleared before
enabling interrupts.
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note
1: Arrows indicate counter increments.
2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the
clock.
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