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| 型号： | RFPIC12F675K-E/SS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDSO20 |
| 封装： | 0.209 INCH, PLASTIC, MO-150, SSOP-20 |
| 文件页数： | 90/123页 |
| 文件大小： | 5438K |
| 代理商： | RFPIC12F675K-E/SS |
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2003 Microchip Technology Inc.
Preliminary
DS70091A-page 67
rfPIC12F675
10.4.1
GP2/INT INTERRUPT
External interrupt on GP2/INT pin is edge-triggered;
either rising if INTEDG bit (OPTION<6>) is set, of
falling, if INTEDG bit is clear. When a valid edge
appears
on
the
GP2/INT
pin,
the
INTF
bit
(INTCON<1>) is set. This interrupt can be disabled by
clearing the INTE control bit (INTCON<4>). The INTF
bit must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The GP2/INT
interrupt can wake-up the processor from SLEEP if the
INTE bit was set prior to going into SLEEP. The status
of the GIE bit decides whether or not the processor
branches to the interrupt vector following wake-up. See
Section 10.9 for details on SLEEP and Figure 10-13 for
timing of wake-up from SLEEP through GP2/INT
interrupt.
10.4.2
TMR0 INTERRUPT
An overflow (FFh
→ 00h) in the TMR0 register will
set the T0IF (INTCON<2>) bit. The interrupt can
be
enabled/disabled
by
setting/clearing
T0IE
(INTCON<5>) bit. For operation of the Timer0 module,
see Section 4.0.
10.4.3
GPIO INTERRUPT
An input change on GPIO change sets the GPIF
(INTCON<0>) bit. The interrupt can be enabled/
disabled by setting/clearing the GPIE (INTCON<3>)
bit. Plus individual pins can be configured through the
IOC register.
10.4.4
COMPARATOR INTERRUPT
See Section 6.9 for description of comparator interrupt.
10.4.5
A/D CONVERTER INTERRUPT
After a conversion is complete, the ADIF flag (PIR<6>)
is set. The interrupt can be enabled/disabled by setting
or clearing ADIE (PIE<6>).
See Section 7.0 for operation of the A/D converter
interrupt.
FIGURE 10-11:
INT PIN INTERRUPT TIMING
Note:
The ANSEL (9Fh) and CMCON (19h)
registers must be initialized to configure an
analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
Note:
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the GPIF inter-
rupt flag may not get set.
Q2
Q1
Q3
Q4
Q2
Q1
Q3
Q4
Q2
Q1
Q3
Q4
Q2
Q1
Q3
Q4
Q2
Q1
Q3
Q4
OSC1
CLKOUT
INT pin
INTF Flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
Interrupt Latency
PC
PC+1
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (PC)
Inst (PC+1)
Inst (PC-1)
Inst (0004h)
Dummy Cycle
Inst (PC)
—
1
4
5
1
2
3
Note
1: INTF flag is sampled here (every Q1).
2: Asynchronous interrupt latency = 3-4 T
CY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in RC Oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
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