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| 型号： | RFPIC12F675K-E/SS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDSO20 |
| 封装： | 0.209 INCH, PLASTIC, MO-150, SSOP-20 |
| 文件页数： | 84/123页 |
| 文件大小： | 5438K |
| 代理商： | RFPIC12F675K-E/SS |
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2003 Microchip Technology Inc.
Preliminary
DS70091A-page 61
rfPIC12F675
10.3.5
BROWN-OUT DETECT (BOD)
The rfPIC12F675 members have on-chip Brown-out
Detect circuitry. A configuration bit, BODEN, can
disable (if clear/programmed) or enable (if set) the
Brown-out Detect circuitry. If V
DD falls below VBOD for
greater than parameter (T
BOD) in Table 13-4 (see
Section 13.0), the Brown-out situation will reset the
device. This will occur regardless of V
DD slew-rate. A
RESET is not guaranteed to occur if V
DD falls below
V
BOD for less than parameter (TBOD).
On any RESET (Power-on, Brown-out, Watchdog,
etc.), the chip will remain in RESET until V
DD rises
above BV
DD (see Figure 10-6). The Power-up Timer
will now be invoked, if enabled, and will keep the chip
in RESET an additional 72 ms.
If V
DD drops below BVDD while the Power-up Timer is
running, the chip will go back into a Brown-out Detect
and the Power-up Timer will be re-initialized. Once V
DD
rises above BV
DD, the Power-up Timer will execute a
72 ms RESET.
FIGURE 10-6:
BROWN-OUT SITUATIONS
10.3.6
TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows: first,
PWRT time-out is invoked after POR has expired.
Then, OST is activated. The total time-out will vary
based on oscillator configuration and PWRTE bit
status. For example, in EC mode with PWRTE bit
erased (PWRT disabled), there will be no time-out at
all. Figure 10-7, Figure 10-8 and Figure 10-9 depict
time-out sequences.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(see Figure 10-8). This is useful for testing purposes or
to synchronize more than one rfPIC12F675 device
operating in parallel.
Table 10-6 shows the RESET conditions for some
special registers, while Table 10-7 shows the RESET
conditions for all the registers.
10.3.7
POWER CONTROL (PCON) STATUS
REGISTER
The
power
CONTROL/STATUS
register,
PCON
(address 8Eh) has two bits.
Bit0 is BOD (Brown-out). BOD is unknown on Power-
on Reset. It must then be set by the user and checked
on subsequent RESETS to see if BOD = 0, indicating
that a brown-out has occurred. The BOD STATUS bit is
a don’t care and is not necessarily predictable if the
brown-out circuit is disabled (by setting BODEN bit = 0
in the Configuration word).
Bit1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
‘1’ to this bit following a Power-on Reset. On a
subsequent RESET, if POR is ‘0’, it will indicate that a
Power-on Reset must have occurred (i.e., V
DD may
have gone too low).
Note:
A Brown-out Detect does not enable the
Power-up Timer if the PWRTE bit in the
configuration word is set.
72 ms(1)
V
BOD
V
DD
Internal
RESET
V
BOD
V
DD
Internal
RESET
72 ms(1)
<72 ms
72 ms(1)
V
BOD
V
DD
Internal
RESET
Note
1: 72 ms delay only if PWRTE bit is programmed to ‘0’.
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