参数资料
型号: RFPIC12F675K-E/SS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDSO20
封装: 0.209 INCH, PLASTIC, MO-150, SSOP-20
文件页数: 82/123页
文件大小: 5438K
代理商: RFPIC12F675K-E/SS
2003 Microchip Technology Inc.
Preliminary
DS70091A-page 59
rfPIC12F675
10.3
RESET
The rfPIC12F675 differentiates between various kinds
of RESET:
a)
Power-on Reset (POR)
b)
WDT Reset during normal operation
c)
WDT Reset during SLEEP
d)
MCLR Reset during normal operation
e)
MCLR Reset during SLEEP
f)
Brown-out Detect (BOD)
Some registers are not affected in any RESET
condition; their status is unknown on POR and
unchanged in any other RESET. Most other registers
are reset to a “RESET state” on:
Power-on Reset
MCLR Reset
WDT Reset
WDT Reset during SLEEP
Brown-out Detect (BOD) Reset
They are not affected by a WDT wake-up, since this is
viewed as the resumption of normal operation. TO and
PD bits are set or cleared differently in different RESET
situations as indicated in Table 10-4. These bits are
used in software to determine the nature of the RESET.
See Table 10-7 for a full description of RESET states of
all registers.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 10-4.
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Table 13-4 in Electrical
Specifications Section for pulse width specification.
FIGURE 10-4:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
R
Q
External
Reset
MCLR/
V
DD
OSC1/
WDT
Module
V
DD Rise
Detect
OST/PWRT
On-chip(1)
RC OSC
WDT
Time-out
Power-on Reset
OST
PWRT
Chip_Reset
10-bit Ripple Counter
Reset
Enable OST
Enable PWRT
SLEEP
See Table 10-3 for time-out situations.
Note
1: This is a separate oscillator from the INTOSC/EC oscillator.
Brown-out
Detect
BODEN
CLKIN
pin
V
PP pin
10-bit Ripple Counter
Q
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