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参数资料
型号： RFPIC12F675K-E/SS
元件分类： 微控制器/微处理器
英文描述： 8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDSO20
封装： 0.209 INCH, PLASTIC, MO-150, SSOP-20
文件页数： 64/123页
文件大小： 5438K
代理商： RFPIC12F675K-E/SS
2003 Microchip Technology Inc.
Preliminary
DS70091A-page 43
rfPIC12F675
7.2
A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (C
HOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 7-3. The source
impedance (R
S) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor C
HOLD. The sampling switch (RSS)
impedance varies over the device voltage (V
DD), see
Figure 7-3. The maximum recommended imped-
ance for analog sources is 10 k
. As the impedance
is decreased, the acquisition time may be decreased.
After the analog input channel is selected (changed),
this acquisition must be done before the conversion
can be started.
To
calculate
the
minimum
acquisition
time,
Equation 7-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D).
The 1/2 LSb error is the maximum error allowed for
the A/D to meet its specified resolution.
To calculate the minimum acquisition time, T
ACQ, see
the
PICmicro
Mid-Range
Reference
Manual
(DS33023).
EQUATION 7-1:
ACQUISITION TIME
FIGURE 7-3:
ANALOG INPUT MODEL
T
ACQ
T
C
T
ACQ
=
Amplifier Settling Time +
Hold Capacitor Charging Time +
Temperature Coefficient
T
AMP + TC + TCOFF
2
s + TC + [(Temperature -25°C)(0.05s/°C)]
C
HOLD (RIC + RSS + RS) In(1/2047)
- 120pF (1k
+ 7k + 10k) In(0.0004885)
16.47
s
2
s + 16.47s + [(50°C -25°C)(0.05s/°C)
19.72
s
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (C
HOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k
. This is required to meet the pin
leakage specification.
C
PIN
VA
R
S
ANx
5 pF
V
DD
V
T = 0.6V
V
T = 0.6V
I
LEAKAGE
R
IC
≤ 1K
Sampling
Switch
SS RSS
C
HOLD
= DAC capacitance
V
SS
6V
Sampling Switch
5V
4V
3V
2V
567 8 9 10 11
(k
)
V
DD
= 120 pF
± 500 nA
Legend
C
PIN
V
T
I
LEAKAGE
R
IC
SS
C
HOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
various junctions
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