APPENDIX A LIST OF I/O REGISTERS
AP-A-2
Seiko Epson Corporation
S1C17651 TECHNICAL MANUAL
Peripheral
Address
Register name
Function
P port &
port MUX
(8-bit device)
0x5200
P0_IN
P0 Port Input Data Register
P0 port input data
0x5201
P0_OUT
P0 Port Output Data Register
P0 port output data
0x5202
P0_OEN
P0 Port Output Enable Register
Enables P0 port outputs.
0x5203
P0_PU
P0 Port Pull-up Control Register
Controls the P0 port pull-up resistor.
0x5205
P0_IMSK
P0 Port Interrupt Mask Register
Enables P0 port interrupts.
0x5206
P0_EDGE
P0 Port Interrupt Edge Select Register
Selects the signal edge for generating P0
port interrupts.
0x5207
P0_IFLG
P0 Port Interrupt Flag Register
Indicates/resets the P0 port interrupt occur-
rence status.
0x5208
P0_CHAT
P0 Port Chattering Filter Control Register
Controls the P0 port chattering filter.
0x5209
P0_KRST
P0 Port Key-Entry Reset Configuration Register Configures the P0 port key-entry reset function.
0x520a
P0_IEN
P0 Port Input Enable Register
Enables P0 port inputs.
0x5210
P1_IN
P1 Port Input Data Register
P1 port input data
0x5211
P1_OUT
P1 Port Output Data Register
P1 port output data
0x5212
P1_OEN
P1 Port Output Enable Register
Enables P1 port outputs.
0x5213
P1_PU
P1 Port Pull-up Control Register
Controls the P1 port pull-up resistor.
0x521a
P1_IEN
P1 Port Input Enable Register
Enables P1 port inputs.
0x52a0
P00_03PMUX P0[3:0] Port Function Select Register
Selects the P0[3:0] port functions.
0x52a1
P04_07PMUX P0[7:4] Port Function Select Register
Selects the P0[7:4] port functions.
0x52a2
P10_13PMUX P1[3:0] Port Function Select Register
Selects the P1[3:0] port functions.
MISC registers
(16-bit device)
0x5322
MISC_
DMODE2
Debug Mode Control Register 2
Enables peripheral operations in debug mode
(except PCLK).
0x5324
MISC_PROT
MISC Protect Register
Enables writing to the MISC registers.
0x5326
MISC_IRAMSZ IRAM Size Select Register
Selects the IRAM size.
0x5328
MISC_TTBRL
Vector Table Address Low Register
Sets vector table address.
0x532a
MISC_TTBRH Vector Table Address High Register
0x532c
MISC_PSR
PSR Register
Indicates the S1C17 Core PSR values.
16-bit PWM
timer Ch.0
(16-bit device)
0x5400
T16A_CTL0
T16A Counter Ch.0 Control Register
Controls the counter.
0x5402
T16A_TC0
T16A Counter Ch.0 Data Register
Counter data
0x5404
T16A_CCCTL0 T16A Comparator/Capture Ch.0 Control
Register
Controls the comparator/capture block and
TOUT.
0x5406
T16A_CCA0
T16A Compare/Capture Ch.0 A Data Register Compare A/capture A data
0x5408
T16A_CCB0
T16A Compare/Capture Ch.0 B Data Register Compare B/capture B data
0x540a
T16A_IEN0
T16A Compare/Capture Ch.0 Interrupt Enable
Register
Enables/disables interrupts.
0x540c
T16A_IFLG0
T16A Compare/Capture Ch.0 Interrupt Flag
Register
Displays/sets interrupt occurrence status.
Flash controller
(16-bit device)
0x54b0
FLASHC_
WAIT
FLASHC Read Wait Control Register
Sets Flash read wait cycle.
Real-time clock
(16-bit device)
0x56c0
RTC_CTL
RTC Control Register
Controls the RTC.
0x56c2
RTC_IEN
RTC Interrupt Enable Register
Enables/disables interrupts.
0x56c4
RTC_IFLG
RTC Interrupt Flag Register
Displays/sets interrupt occurrence status.
0x56c6
RTC_MS
RTC Minute/Second Counter Register
Minute/second counter data
0x56c8
RTC_H
RTC Hour Counter Register
Hour counter data
Core I/O Reserved Area (0xffff84–0xffffd0)
Peripheral
Address
Register name
Function
S1C17 Core
I/O
0xffff84
IDIR
Processor ID Register
Indicates the processor ID.
0xffff90
DBRAM
Debug RAM Base Register
Indicates the debug RAM base address.
0xffffa0
DCR
Debug Control Register
Controls debugging.
0xffffb4
IBAR1
Instruction Break Address Register 1
Sets Instruction break address #1.
0xffffb8
IBAR2
Instruction Break Address Register 2
Sets Instruction break address #2.
0xffffbc
IBAR3
Instruction Break Address Register 3
Sets Instruction break address #3.
0xffffd0
IBAR4
Instruction Break Address Register 4
Sets Instruction break address #4.
Note: Addresses marked as “Reserved” or unused peripheral circuit areas not marked in the table must
not be accessed by application programs.