APPENDIX A LIST OF I/O REGISTERS
AP-A-12
Seiko Epson Corporation
S1C17651 TECHNICAL MANUAL
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
T16A Counter
Ch.0 Data
Register
(T16A_TC0)
0x5402
(16 bits)
D15–0 T16ATC
[15:0]
Counter data
T16ATC15 = MSB
T16ATC0 = LSB
0x0 to 0xffff
0x0
R
T16A
Comparator/
Capture Ch.0
Control Register
(T16A_CCCTL0)
0x5404
(16 bits)
D15–14 CAPBTRG
[1:0]
Capture B trigger select
CAPBTRG[1:0] Trigger edge
0x0 R/W
0x3
0x2
0x1
0x0
↑ and ↓
↓
↑
None
D13–12 TOUTBMD
[1:0]
TOUT B mode select
TOUTBMD[1:0]
Mode
0x0 R/W
0x3
0x2
0x1
0x0
cmp B:
↑ or ↓
cmp A:
↑ or ↓
cmp A:
↑, B: ↓
Off
D11–10 –
reserved
–
0 when being read.
D9
TOUTBINV TOUT B invert
1 Invert
0 Normal
0
R/W
D8
CCBMD
T16A_CCB register mode select
1 Capture
0 Comparator
0
R/W
D7–6 CAPATRG
[1:0]
Capture A trigger select
CAPATRG[1:0] Trigger edge
0x0 R/W
0x3
0x2
0x1
0x0
↑ and ↓
↓
↑
None
D5–4 TOUTAMD
[1:0]
TOUT A mode select
TOUTAMD[1:0]
Mode
0x0 R/W
0x3
0x2
0x1
0x0
cmp B:
↑ or ↓
cmp A:
↑ or ↓
cmp A:
↑, B: ↓
Off
D3–2 –
reserved
–
0 when being read.
D1
TOUTAINV TOUT A invert
1 Invert
0 Normal
0
R/W
D0
CCAMD
T16A_CCA register mode select
1 Capture
0 Comparator
0
R/W
T16A
Comparator/
Capture Ch.0 A
Data Register
(T16A_CCA0)
0x5406
(16 bits)
D15–0 CCA[15:0] Compare/capture A data
CCA15 = MSB
CCA0 = LSB
0x0 to 0xffff
0x0 R/W
T16A
Comparator/
Capture Ch.0 B
Data Register
(T16A_CCB0)
0x5408
(16 bits)
D15–0 CCB[15:0] Compare/capture B data
CCB15 = MSB
CCB0 = LSB
0x0 to 0xffff
0x0 R/W
T16A
Comparator/
Capture Ch.0
Interrupt Enable
Register
(T16A_IEN0)
0x540a
(16 bits)
D15–6 –
reserved
–
0 when being read.
D5
CAPBOWIE Capture B overwrite interrupt enable 1 Enable
0 Disable
0
R/W
D4
CAPAOWIE Capture A overwrite interrupt enable 1 Enable
0 Disable
0
R/W
D3
CAPBIE
Capture B interrupt enable
1 Enable
0 Disable
0
R/W
D2
CAPAIE
Capture A interrupt enable
1 Enable
0 Disable
0
R/W
D1
CBIE
Compare B interrupt enable
1 Enable
0 Disable
0
R/W
D0
CAIE
Compare A interrupt enable
1 Enable
0 Disable
0
R/W
T16A
Comparator/
Capture Ch.0
Interrupt Flag
Register
(T16A_IFLG0)
0x540c
(16 bits)
D15–6 –
reserved
–
0 when being read.
D5
CAPBOWIF Capture B overwrite interrupt flag 1 Cause of
interrupt
occurred
0 Cause of
interrupt not
occurred
0
R/W Reset by writing 1.
D4
CAPAOWIF Capture A overwrite interrupt flag
0
R/W
D3
CAPBIF
Capture B interrupt flag
0
R/W
D2
CAPAIF
Capture A interrupt flag
0
R/W
D1
CBIF
Compare B interrupt flag
0
R/W
D0
CAIF
Compare A interrupt flag
0
R/W
0x54b0
Flash Controller
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
FLASHC Read
Wait Control
Register
(FLASHC_
WAIT)
0x54b0
(16 bits)
D15–8 –
reserved
–
0 when being read.
D7
–
reserved
–
X
–
X when being read.
D6-2 –
reserved
–
0 when being read.
D1–0 RDWAIT
[1:0]
Flash read wait cycle
RDWAIT[1:0]
Wait
0x3 R/W
0x3
0x2
0x1
0x0
3 wait
2 wait
1 wait
No wait
0x56c0–0x56c8
Real-time Clock
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
RTC Control
Register
(RTC_CTL)
0x56c0
(16 bits)
D15–9 –
reserved
–
0 when being read.
D8
RTCST
RTC run/stop status
1 Running
0 Stop
0
R
D7–6 –
reserved
–
0 when being read.
D5
BCDMD
BCD mode select
1 BCD mode 0 Binary mode
0
R/W
D4
RTC24H
24H/12H mode select
1 12H
0 24H
0
R/W
D3–1 –
reserved
–
0 when being read.
D0
RTCRUN
RTC run/stop control
1 Run
0 Stop
0
R/W