2 CPU
S1C17651 TECHNICAL MANUAL
Seiko Epson Corporation
2-5
Classification
Mnemonic
Function
Branch
retd
Return from debug processing
System control
nop
No operation
halt
HALT mode
slp
SLEEP mode
ei
Enable interrupts
di
Disable interrupts
Coprocessor control ld.cw
%rd,%rs
Transfer data to coprocessor
%rd,imm7
ld.ca
%rd,%rs
Transfer data to coprocessor and get results and ag statuses
%rd,imm7
ld.cf
%rd,%rs
Transfer data to coprocessor and get ag statuses
%rd,imm7
*1 The ld.a instruction accesses memories in 32-bit length. During data transfer from a register to a memory, the
32-bit data in which the eight high-order bits are set to 0 is written to the memory. During reading from a memory,
the eight high-order bits of the read data are ignored.
The symbols in the above table each have the meanings specified below.
3.2 Symbol Meanings
Table 2.
Symbol
Description
%rs
General-purpose register, source
%rd
General-purpose register, destination
[%rb]
Memory addressed by general-purpose register
[%rb]+
Memory addressed by general-purpose register with address post-incremented
[%rb]-
Memory addressed by general-purpose register with address post-decremented
-[%rb]
Memory addressed by general-purpose register with address pre-decremented
%sp
Stack pointer
[%sp],[%sp+imm7]
Stack
[%sp]+
Stack with address post-incremented
[%sp]-
Stack with address post-decremented
-[%sp]
Stack with address pre-decremented
imm3,imm5,imm7,imm13
Unsigned immediate (numerals indicating bit length)
sign7,sign10
Signed immediate (numerals indicating bit length)
Reading PSR
2.4
The S1C17651 includes the MISC_PSR register for reading the contents of the PSR (Processor Status Register) in
the S1C17 Core. Reading the contents of this register makes it possible to check the contents of the PSR using the
application software. Note that data cannot be written to the PSR.
PSR Register (MISC_PSR)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
PSR Register
(MISC_PSR)
0x532c
(16 bits)
D15–8 –
reserved
–
0 when being read.
D7–5 PSRIL[2:0] PSR interrupt level (IL) bits
0x0 to 0x7
0x0
R
D4
PSRIE
PSR interrupt enable (IE) bit
1 1 (enable)
0 0 (disable)
0
R
D3
PSRC
PSR carry (C) flag
1 1 (set)
0 0 (cleared)
0
R
D2
PSRV
PSR overflow (V) flag
1 1 (set)
0 0 (cleared)
0
R
D1
PSRZ
PSR zero (Z) flag
1 1 (set)
0 0 (cleared)
0
R
D0
PSRN
PSR negative (N) flag
1 1 (set)
0 0 (cleared)
0
R
D[15:8]
Reserved
D[7:5]
PSRIL[2:0]: PSR Interrupt Level (IL) Bits
The value of the PSR IL (interrupt level) bits can be read out. (Default: 0x0)
D4
PSRIE: PSR Interrupt Enable (IE) Bit
The value of the PSR IE (interrupt enable) bit can be read out.
1 (R):
1 (interrupt enabled)
0 (R):
0 (interrupt disabled) (default)