7 CLOCK GENERATOR (CLG)
S1C17651 TECHNICAL MANUAL
Seiko Epson Corporation
7-15
Oscillation Stabilization Wait Control Register (CLG_WAIT)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
Oscillation
Stabilization
Wait Control
Register
(CLG_WAIT)
0x507d
(8 bits)
D7–6 OSC3BWT
[1:0]
OSC3B stabilization wait cycle
select
OSC3BWT[1:0]
Wait cycle
0x0 R/W
0x3
0x2
0x1
0x0
8 cycles
16 cycles
32 cycles
64 cycles
D5–4 OSC3AWT
[1:0]
OSC3A stabilization wait cycle
select
OSC3AWT[1:0]
Wait cycle
0x0 R/W
0x3
0x2
0x1
0x0
128 cycles
256 cycles
512 cycles
1024 cycles
D3–2 OSC1BWT
[1:0]
OSC1B stabilization wait cycle
select
OSC1BWT[1:0]
Wait cycle
0x0 R/W
0x3
0x2
0x1
0x0
8 cycles
16 cycles
32 cycles
64 cycles
D1–0 OSC1AWT
[1:0]
OSC1A stabilization wait cycle
select
OSC1AWT[1:0]
Wait cycle
0x0 R/W
0x3
0x2
0x1
0x0
2048 cycles
4096 cycles
8192 cycles
16384 cycles
D[7:6]
OSC3BWT[1:0]: OSC3B Stabilization Wait Cycle Select Bits
An oscillation stabilization wait time is set to prevent malfunctions due to unstable clock operations
at the start of OSC3B oscillation. The OSC3B clock is not supplied to the system immediately after
OSC3B oscillation starts until the time set here has elapsed.
8.9 OSC3B Oscillation Stabilization Wait Time Settings
Table 7.
OSC3BWT[1:0]
Oscillation stabilization wait time
0x3
8 cycles
0x2
16 cycles
0x1
32 cycles
0x0
64 cycles
(Default: 0x0)
This is set to 64 cycles (OSC3B clock) after an initial reset. This means the CPU can start operating
when the CPU operation start time at initial reset indicated below (at a maximum) has elapsed after the
reset state is canceled.
CPU operation start time at initial reset
≤ OSC3B oscillation start time (max.) + OSC3B
oscillation stabilization wait time (64 cycles)
When the system clock is switched to OSC3B immediately after turning the OSC3B oscillator on, the
OSC3B clock is supplied to the system after the OSC3B clock system supply wait time indicated be-
low (at a maximum) has elapsed. If the power supply voltage VDD has stabilized sufficiently, OSC3B-
WT[1:0] can be set to 0x3 to reduce the oscillation stabilization wait time.
OSC3B clock system supply wait time
≤ OSC3B oscillation start time (max.) + OSC3B os-
cillation stabilization wait time
D[5:4]
OSC3AWT[1:0]: OSC3A Stabilization Wait Cycle Select Bits
An oscillation stabilization wait time is set to prevent malfunctions due to unstable clock operation
at the start of OSC3A oscillation. The OSC3A clock is not supplied to the system immediately after
OSC3A oscillation starts until the time set here has elapsed.
8.10 OSC3A Oscillation Stabilization Wait Time Settings
Table 7.
OSC3AWT[1:0]
Oscillation stabilization wait time
0x3
128 cycles
0x2
256 cycles
0x1
512 cycles
0x0
1024 cycles
(Default: 0x0)