19 SUPPLY VOLTAGE DETECTION CIRCUIT (SVD)
19-2
Seiko Epson Corporation
S1C17651 TECHNICAL MANUAL
SVD Control
19.3
Power supply voltage detection using the SVD circuit is initiated by writing 1 to SVDEN/SVD_EN register. Af-
ter that, the supply voltage detection results can be read out from SVDDT/SVD_RSLT register. By writing 0 to
SVDEN, the SVD circuit sets the detection result at that point to SVDDT and stops detection.
The detection results and SVDDT readings are as follows.
When power supply voltage (VDD)
≥ comparison voltage: SVDDT = 0
When power supply voltage (VDD) < comparison voltage: SVDDT = 1
Notes: An SVD circuit-enable response time is required to obtain stable detection results after
SVDEN is altered from 0 to 1. Also when SVDC[4:0] is altered, an SVD circuit response time
is required to obtain stable detection results. Wait until the response time has elapsed before
reading SVDDT. Also when reading the detection results after stopping the SVD circuit,
SVDEN should be set to 0 after the response time has elapsed. For these response times,
see “Electrical Characteristics.”
Operating the SVD circuit increases current consumption. If power supply voltage detection is
not required, stop SVD operations by setting SVDEN to 0.
Control Register Details
19.4
4.1 List of SVD Registers
Table 19.
Address
Register name
Function
0x5100
SVD_EN
SVD Enable Register
Enables/disables the SVD operation.
0x5101
SVD_CMP
SVD Comparison Voltage Register
Sets the comparison voltage.
0x5102
SVD_RSLT
SVD Detection Result Register
Voltage detection results
The SVD module registers are described in detail below.
Note: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1.
SVD Enable Register (SVD_EN)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
SVD Enable
Register
(SVD_EN)
0x5100
(8 bits)
D7–1 –
reserved
–
0 when being read.
D0
SVDEN
SVD enable
1 Enable
0 Disable
0
R/W
D[7:1]
Reserved
D0
SVDEN: SVD Enable Bit
Enables or disables SVD operations.
1 (R/W): Enabled
0 (R/W): Disabled (default)
Setting SVDEN to 1 initiates power supply voltage detection; setting to 0 stops detection after loading
the detection results to SVDDT/SVD_RSLT register.
Notes: An SVD circuit-enable response time is required to obtain stable detection results after
SVDEN is altered from 0 to 1. Also when SVDC[4:0] is altered, an SVD circuit response
time is required to obtain stable detection results. Wait until the response time has elapsed
before reading SVDDT. Also when reading the detection results after stopping the SVD
circuit, SVDEN should be set to 0 after the response time has elapsed. For these response
times, see “Electrical Characteristics.”
Operating the SVD circuit increases current consumption. If power supply voltage detection
is not required, stop SVD operations by setting SVDEN to 0.