APPENDIX A LIST OF I/O REGISTERS
S1C17651 TECHNICAL MANUAL
Seiko Epson Corporation
AP-A-9
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
Buzzer
Duty Ratio
Control Register
(SND_BZDT)
0x5182
(8 bits)
D7–3 –
reserved
–
0 when being read.
D2–0 BZDT[2:0]
Buzzer duty ratio select
BZDT[2:0]
Duty (volume) 0x0 R/W
0x7
:
0x0
Level 8 (Min.)
:
Level 1 (Max.)
0x5200–0x52a2
P Port & Port MUX
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
P0 Port Input
Data Register
(P0_IN)
0x5200
(8 bits)
D7–0 P0IN[7:0]
P0[7:0] port input data
1 1 (H)
0 0 (L)
×
R
P0 Port Output
Data Register
(P0_OUT)
0x5201
(8 bits)
D7–0 P0OUT[7:0] P0[7:0] port output data
1 1 (H)
0 0 (L)
0
R/W
P0 Port
Output Enable
Register
(P0_OEN)
0x5202
(8 bits)
D7–0 P0OEN[7:0] P0[7:0] port output enable
1 Enable
0 Disable
0
R/W
P0 Port Pull-up
Control Register
(P0_PU)
0x5203
(8 bits)
D7–0 P0PU[7:0]
P0[7:0] port pull-up enable
1 Enable
0 Disable
1
(0xff)
R/W
P0 Port
Interrupt Mask
Register
(P0_IMSK)
0x5205
(8 bits)
D7–0 P0IE[7:0]
P0[7:0] port interrupt enable
1 Enable
0 Disable
0
R/W
P0 Port
Interrupt Edge
Select Register
(P0_EDGE)
0x5206
(8 bits)
D7–0 P0EDGE[7:0] P0[7:0] port interrupt edge select
1 Falling edge 0 Rising edge
0
R/W
P0 Port
Interrupt Flag
Register
(P0_IFLG)
0x5207
(8 bits)
D7–0 P0IF[7:0]
P0[7:0] port interrupt flag
1 Cause of
interrupt
occurred
0 Cause of
interrupt not
occurred
0
R/W Reset by writing 1.
P0 Port
Chattering
Filter Control
Register
(P0_CHAT)
0x5208
(8 bits)
D7
–
reserved
–
0 when being read.
D6–4 P0CF2[2:0] P0[7:4] chattering filter time
P0CF2[2:0]
Filter time
0
R/W
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
16384/fPCLK
8192/fPCLK
4096/fPCLK
2048/fPCLK
1024/fPCLK
512/fPCLK
256/fPCLK
None
0x0 R/W
D3
–
reserved
–
0 when being read.
D2–0 P0CF1[2:0] P0[3:0] chattering filter time
P0CF1[2:0]
Filter time
0x0 R/W
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
16384/fPCLK
8192/fPCLK
4096/fPCLK
2048/fPCLK
1024/fPCLK
512/fPCLK
256/fPCLK
None
P0 Port Key-
Entry Reset
Configuration
Register
(P0_KRST)
0x5209
(8 bits)
D7–2 –
reserved
–
0 when being read.
D1–0 P0KRST[1:0] P0 port key-entry reset
configuration
P0KRST[1:0]
Configuration 0x0 R/W
0x3
0x2
0x1
0x0
P0[3:0] = 0
P0[2:0] = 0
P0[1:0] = 0
Disable
P0 Port Input
Enable Register
(P0_IEN)
0x520a
(8 bits)
D7–0 P0IEN[7:0] P0[7:0] port input enable
1 Enable
0 Disable
1
(0xff)
R/W
P1 Port Input
Data Register
(P1_IN)
0x5210
(8 bits)
D7–4 –
reserved
–
0 when being read.
D3–0 P1IN[3:0]
P1[3:0] port input data
1 1 (H)
0 0 (L)
×
R
P1 Port Output
Data Register
(P1_OUT)
0x5211
(8 bits)
D7–4 –
reserved
–
0 when being read.
D3–0 P1OUT[3:0] P1[3:0] port output data
1 1 (H)
0 0 (L)
0
R/W
P1 Port
Output Enable
Register
(P1_OEN)
0x5212
(8 bits)
D7–4 –
reserved
–
0 when being read.
D3–0 P1OEN[3:0] P1[3:0] port output enable
1 Enable
0 Disable
0
R/W