14 WATCHDOG TIMER (WDT)
14-2
Seiko Epson Corporation
S1C17651 TECHNICAL MANUAL
WDT Run/Stop Control
14.3.2
WDT starts counting when a value other than 0b1010 is written to WDTRUN[3:0]/WDT_CTL register and stops
when 0b1010 is written.
At initial reset, WDTRUN[3:0] is set to 0b1010 to stop the watchdog timer.
Since an NMI or reset may be generated immediately after running depending on the counter value, WDT should
also be reset concurrently (before running the watchdog timer), as explained in the following section.
WDT Reset
14.3.3
To reset WDT, write 1 to WDTRST/WDT_CTL register.
A location should be provided for periodically processing the routine for resetting WDT before an NMI or reset
is generated when using WDT. Process this routine within 131,072/fOSC1 second (4 seconds when fOSC1 = 32.768
kHz) cycle.
After resetting, WDT starts counting with a new NMI/Reset generation cycle.
If WDT is not reset within the NMI/Reset generation cycle for any reason, the CPU is switched to interrupt pro-
cessing by NMI or reset, the interrupt vector is read out, and the interrupt handler routine is executed. The reset and
NMI vector addresses are TTBR + 0x0 and TTBR + 0x08.
If the counter overflows and generates an NMI without WDT being reset, WDTST/WDT_ST register is set to 1.
This bit is provided to confirm that WDT was the source of the NMI. The WDTST set to 1 is cleared to 0 by reset-
ting WDT.
Operations in HALT and SLEEP Modes
14.3.4
HALT mode
The WDT module operates in HALT mode, as the clock is supplied. HALT mode is therefore cleared by an NMI or
reset if it continues for more than the NMI/reset generation cycle. To disable WDT while in HALT mode, stop WDT
by writing 0b1010 to WDTRUN[3:0]/WDT_CTL register before executing the halt instruction. Reset WDT before
resuming operations after HALT mode is cleared.
SLEEP mode
The clock supplied from the CLG module is stopped in SLEEP mode, which also stops WDT. To prevent generation
of an unnecessary NMI or reset after clearing SLEEP mode, reset WDT before executing the slp instruction. WDT
should also be stopped as required using WDTRUN[3:0].
Control Register Details
14.4
Table 14.4.1 List of WDT Registers
Address
Register name
Function
0x5040
WDT_CTL
Watchdog Timer Control Register
Resets and starts/stops the timer.
0x5041
WDT_ST
Watchdog Timer Status Register
Sets the timer mode and indicates NMI status.
The WDT registers are described in detail below.
Note: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1.
Watchdog Timer Control Register (WDT_CTL)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
Watchdog
Timer Control
Register
(WDT_CTL)
0x5040
(8 bits)
D7–5 –
reserved
–
0 when being read.
D4
WDTRST
Watchdog timer reset
1 Reset
0 Ignored
0
W
D3–0 WDTRUN[3:0] Watchdog timer run/stop control
Other than 1010
Run
1010
Stop
1010 R/W
D[7:5]
Reserved