10 I/O PORTS (P)
S1C17651 TECHNICAL MANUAL
Seiko Epson Corporation
10-7
PxPUy is the pull-up control bit that corresponds directly to the Pxy port. Setting to 1 enables the pull-
up resistor and the port pin will be pulled up when output is disabled (PxOENy = 0). When PxPUy is set
to 0, the pin will not be pulled up. When output is enabled (PxOENy = 1), the PxPUy setting is ignored,
and the pin is not pulled up. I/O ports that are not used should be set with pull-up enabled. The PxPUy
setting is also ignored if a pin function other than Pxy I/O port is selected. In this case, the pull-up resis-
tor is automatically enabled/disabled according to the pin function selected.
P0 Port Interrupt Mask Register (P0_IMSK)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
P0 Port
Interrupt Mask
Register
(P0_IMSK)
0x5205
(8 bits)
D7–0 P0IE[7:0]
P0[7:0] port interrupt enable
1 Enable
0 Disable
0
R/W
Note: This register is available for the P0 ports.
D[7:0]
P0IE[7:0]: P0[7:0] Port Interrupt Enable Bits
Enables or disables each port interrupt.
1 (R/W): Interrupt enabled
0 (R/W): Interrupt disabled (default)
Setting P0IEy to 1 enables the corresponding P0y port input interrupt, while setting to 0 disables the in-
terrupt. Status changes for the input pins with interrupt disabled do not affect interrupt occurrence.
P0 Port Interrupt Edge Select Register (P0_EDGE)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
P0 Port
Interrupt Edge
Select Register
(P0_EDGE)
0x5206
(8 bits)
D7–0 P0EDGE[7:0] P0[7:0] port interrupt edge select
1 Falling edge 0 Rising edge
0
R/W
Note: This register is available for the P0 ports.
D[7:0]
P0EDGE[7:0]: P0[7:0] Port Interrupt Edge Select Bits
Selects the input signal edge for generating each port interrupt.
1 (R/W): Falling edge
0 (R/W): Rising edge (default)
Port interrupts are generated at the input signal falling edge when P0EDGEy is set to 1 and at the rising
edge when set to 0.
P0 Port Interrupt Flag Register (P0_IFLG)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
P0 Port
Interrupt Flag
Register
(P0_IFLG)
0x5207
(8 bits)
D7–0 P0IF[7:0]
P0[7:0] port interrupt flag
1 Cause of
interrupt
occurred
0 Cause of
interrupt not
occurred
0
R/W Reset by writing 1.
Note: This register is available for the P0 ports.
D[7:0]
P0IF[7:0]: P0[7:0] Port Interrupt Flag Bits
These are interrupt flags indicating the interrupt cause occurrence status.
1 (R):
Interrupt cause occurred
0 (R):
No interrupt cause occurred (default)
1 (W):
Reset flag
0 (W):
Ignored
P0IFy is the interrupt flag corresponding to the individual eight P0 ports. It is set to 1 at the specified
edge (rising or falling edge) of the input signal. When the corresponding P0IEy/P0_IMSK register has
been set to 1, a port interrupt request signal is also output to the ITC at the same time. An interrupt is
generated if the ITC and S1C17 Core interrupt conditions are satisfied.