APPENDIX A LIST OF I/O REGISTERS
S1C17651 TECHNICAL MANUAL
Seiko Epson Corporation
AP-A-13
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
RTC Interrupt
Enable Register
(RTC_IEN)
0x56c2
(16 bits)
D15–10 –
reserved
–
0 when being read.
D9
INT1DEN
1-day interrupt enable
1 Enable
0 Disable
0
R/W
D8
INTHDEN
Half-day interrupt enable
1 Enable
0 Disable
0
R/W
D7
INT1HEN
1-hour interrupt enable
1 Enable
0 Disable
0
R/W
D6
INT10MEN 10-minute interrupt enable
1 Enable
0 Disable
0
R/W
D5
INT1MEN
1-minute interrupt enable
1 Enable
0 Disable
0
R/W
D4
INT10SEN 10-second interrupt enable
1 Enable
0 Disable
0
R/W
D3
INT1HZEN 1 Hz interrupt enable
1 Enable
0 Disable
0
R/W
D2
INT4HZEN 4 Hz interrupt enable
1 Enable
0 Disable
0
R/W
D1
INT8HZEN 8 Hz interrupt enable
1 Enable
0 Disable
0
R/W
D0
INT32HZEN 32 Hz interrupt enable
1 Enable
0 Disable
0
R/W
RTC Interrupt
Flag Register
(RTC_IFLG)
0x56c4
(16 bits)
D15–10 –
reserved
–
0 when being read.
D9
INT1D
1-day interrupt flag
1 Cause of
interrupt
occurred
0 Cause of
interrupt not
occurred
0
R/W Reset by writing 1.
D8
INTHD
Half-day interrupt flag
0
R/W
D7
INT1H
1-hour interrupt flag
0
R/W
D6
INT10M
10-minute interrupt flag
0
R/W
D5
INT1M
1-minute interrupt flag
0
R/W
D4
INT10S
10-second interrupt flag
0
R/W
D3
INT1HZ
1 Hz interrupt flag
0
R/W
D2
INT4HZ
4 Hz interrupt flag
0
R/W
D1
INT8HZ
8 Hz interrupt flag
0
R/W
D0
INT32HZ
32 Hz interrupt flag
0
R/W
RTC
Minute/Second
Counter
Register
(RTC_MS)
0x56c6
(16 bits)
D15
–
reserved
–
0 when being read.
D14–8 RTCMIN
[6:0]
Minute counter
0x0 to 0x3b (binary mode)
0x00 to 0x59 (BCD mode)
X
R/W
D7
–
reserved
–
0 when being read.
D6–0 RTCSEC
[6:0]
Second counter
0x0 to 0x3b (binary mode)
0x00 to 0x59 (BCD mode)
X
R/W
RTC
Hour Counter
Register
(RTC_H)
0x56c8
(16 bits)
D15–8 –
reserved
–
0 when being read.
D7
AMPM
AM/PM
1 PM
0 AM
X
R/W
D6
–
reserved
–
0 when being read.
D5–0 RTCHOUR
[5:0]
Hour counter
0x0 to 0x17 (binary mode)
0x00 to 0x23 (BCD mode)
X
R/W
0xffff84–0xffffd0
S1C17 Core I/O
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
Processor ID
Register
(IDIR)
0xffff84
(8 bits)
D7–0 IDIR[7:0]
Processor ID
0x10: S1C17 Core
0x10
R
Debug RAM
Base Register
(DBRAM)
0xffff90
(32 bits)
D31–24 –
Unused (fixed at 0)
0x0
R
D23–0 DBRAM[23:0] Debug RAM base address
0x7c0
0x7c0 R
Debug Control
Register
(DCR)
0xffffa0
(8 bits)
D7
IBE4
Instruction break #4 enable
1 Enable
0 Disable
0
R/W
D6
IBE3
Instruction break #3 enable
1 Enable
0 Disable
0
R/W
D5
IBE2
Instruction break #2 enable
1 Enable
0 Disable
0
R/W
D4
DR
Debug request flag
1 Occurred
0 Not occurred
0
R/W Reset by writing 1.
D3
IBE1
Instruction break #1 enable
1 Enable
0 Disable
0
R/W
D2
IBE0
Instruction break #0 enable
1 Enable
0 Disable
0
R/W
D1
SE
Single step enable
1 Enable
0 Disable
0
R/W
D0
DM
Debug mode
1 Debug mode 0 User mode
0
R
Instruction
Break Address
Register 1
(IBAR1)
0xffffb4
(32 bits)
D31–24 –
reserved
–
0 when being read.
D23–0 IBAR1[23:0] Instruction break address #1
IBAR123 = MSB
IBAR10 = LSB
0x0 to 0xffffff
0x0 R/W
Instruction
Break Address
Register 2
(IBAR2)
0xffffb8
(32 bits)
D31–24 –
reserved
–
0 when being read.
D23–0 IBAR2[23:0] Instruction break address #2
IBAR223 = MSB
IBAR20 = LSB
0x0 to 0xffffff
0x0 R/W
Instruction
Break Address
Register 3
(IBAR3)
0xffffbc
(32 bits)
D31–24 –
reserved
–
0 when being read.
D23–0 IBAR3[23:0] Instruction break address #3
IBAR323 = MSB
IBAR30 = LSB
0x0 to 0xffffff
0x0 R/W
Instruction
Break Address
Register 4
(IBAR4)
0xffffd0
(32 bits)
D31–24 –
reserved
–
0 when being read.
D23–0 IBAR4[23:0] Instruction break address #4
IBAR423 = MSB
IBAR40 = LSB
0x0 to 0xffffff
0x0 R/W