8 THEORETICAL REGULATION (TR)
8-2
Seiko Epson Corporation
S1C17651 TECHNICAL MANUAL
3.1.1 Regulation Value Settings
Table 8.
TRIM[4:0]
Amount of correction/
one adjustment
(n/32768)
Rate *
(Seconds/Day)
TRIM[4:0]
Amount of correction/
one adjustment
(n/32768)
Rate *
(Seconds/Day)
0x10
-15
+3.955
0x00
+1
-0.264
0x11
-14
+3.691
0x01
+2
-0.527
0x12
-13
+3.428
0x02
+3
-0.791
0x13
-12
+3.164
0x03
+4
-1.055
0x14
-11
+2.900
0x04
+5
-1.318
0x15
-10
+2.637
0x05
+6
-1.582
0x16
-9
+2.373
0x06
+7
-1.846
0x17
-8
+2.109
0x07
+8
-2.109
0x18
-7
+1.846
0x08
+9
-2.373
0x19
-6
+1.582
0x09
+10
-2.637
0x1a
-5
+1.318
0x0a
+11
-2.900
0x1b
-4
+1.055
0x0b
+12
-3.164
0x1c
-3
+0.791
0x0c
+13
-3.428
0x1d
-2
+0.527
0x0d
+14
-3.691
0x1e
-1
+0.264
0x0e
+15
-3.955
0x1f
0
0x0f
+16
-4.219
* Rates when theoretical regulation is executed in 10-second cycles
(Default: 0x0)
Addresses 0xbffa to 0xbffb in the Flash memory are reserved for storing the correction value. The correction value
should be programmed in this area by the user and use it for setting TRIM[4:0]. The IC will be shipped with this
area emptied, therefore, do not place any program code or data in these addresses.
Executing Theoretical Regulation
8.3.2
Writing 1 to REGTRIG/TR_CTL register starts theoretical regulation that is performed in the OSC1A clock (32.768
kHz) divider. This operation extends or reduces the cycle time of the 256 Hz clock output by the OSC1A divider
for the regulation value specified by TRIM[4:0]. Theoretical regulation is performed only once by writing 1 to
REGTRIG. To perform theoretical regulation periodically, use a timer interrupt handler to write 1 to REGTRIG.
Note that a maximum 16.6 ms of delay occurs before theoretical regulation actually starts after writing to
REGTRIG. Writing 1 to REGTRIG in this period is ineffective, so to write 1 to REGTRIG successively, an interval
at least 16.6 ms is necessary between writings.
The regulated clock (F256) will be supplied to the OSC1 peripheral circuits such as the clock timer.
Note: Use an interrupt from a peripheral timer module that runs with the regulated clock (F256) to ex-
ecute theoretical regulation. An interrupt from the timer that runs all the time should be used to
reduce current consumption.
Regulated Clock External Monitor
8.3.3
Either the 256 Hz (F256) or 1 Hz (F1) regulated clock can be output from the REGMON pin for monitoring.
RCLKFSEL/TR_CTL register is used to select the clock to be monitored from F256 and F1. When RCLKFSEL is
0 (default), F256 is selected; when RCLKFSEL is set to 1, F1 is selected.
The selected clock is output from the REGMON pin by setting RCLKMON to 1. Setting RCLKMON to 0 stops the
clock output and the REGMON pin goes low (VSS) level.
Notes: Before the 256 Hz regulated clock can be monitored, either the clock timer (CT) or watchdog
timer (WDT) must be turned on. Or turn the 16-bit PWM timer (T16A2) on after F256 (256 Hz
regulated clock) is selected as its clock.
Before the 1 Hz regulated clock can be monitored, the real-time clock (RTC) must be turned
on.