3 MEMORY MAP, BUS CONTROL
3-2
Seiko Epson Corporation
S1C17651 TECHNICAL MANUAL
* Handling the eight high-order bits during 32-bit accesses
The size of the S1C17 Core general-purpose registers is 24 bits.
During writing, the eight high-order bits are written as 0. During reading from a memory, the eight high-order
bits are ignored. However, the stack operation in an interrupt handling reads/writes 32-bit data that consists of the
PSR value as the high-order 8 bits and the return address as the low order 24 bits.
For more information, refer to the “S1C17 Core Manual.”
Restrictions on Access Size
3.1.1
The peripheral modules can be accessed with an 8-bit, 16-bit, or 32-bit instruction. However, reading for an unnec-
essary register may change the peripheral module status and it may cause a problem. Therefore, use the appropriate
instructions according to the device size.
Restrictions on Instruction Execution Cycles
3.1.2
An instruction fetch and a data access are not performed simultaneously under one of the conditions listed below.
This prolongs the instruction fetch cycle for the number of data area bus cycles.
When the S1C17651 executes the instruction stored in the Flash area and accesses data in the Flash area
When the S1C17651 executes the instruction stored in the internal RAM area and accesses data in the internal
RAM area
Flash Area
3.2
Embedded Flash Memory
3.2.1
The 16K-byte area from address 0x8000 to address 0xbfff contains a Flash memory (4K bytes
× 4 sectors) for stor-
ing application programs and data. Address 0x8000 is defined as the vector table base address, therefore a vector
table (see “Vector Table” in the “Interrupt Controller (ITC)” chapter) must be placed from the beginning of the
area. The vector table base address can be modified with the MISC_TTBRL/MISC_TTBRH registers.
Flash Programming
3.2.2
The S1C17651 supports on-board programming of the Flash memory, it makes it possible to program the Flash
memory with the application programs/data by using the debugger through an ICDmini.
Protect Bits
3.2.3
In order to protect the memory contents, the Flash memory provides two protection features, write protection and
data read protection, that can be configured for every 4K-byte areas. The write protection disables writing data to
the configured area and erasing the sectors (except the sector that includes the protect bits). The data-read protec-
tion disables reading data from the configured area (the read value is always 0x0000). However, it does not disable
the instruction fetch operation by the CPU. The Flash memory provides the protect bits listed below. Program the
protect bit corresponding to the area to be protected to 0. The protection can only be disabled using the debugger.