APPENDIX A LIST OF I/O REGISTERS
S1C17651 TECHNICAL MANUAL
Seiko Epson Corporation
AP-A-11
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
Debug Mode
Control
Register 2
(MISC_DMODE2)
0x5322
(16 bits)
D15–1 –
reserved
–
0 when being read.
D0
DBRUN2
Run/stop select in debug mode
(except PCLK peripheral circuits)
1 Run
0 Stop
0
R/W
MISC Protect
Register
(MISC_PROT)
0x5324
(16 bits)
D15–0 PROT[15:0] MISC register write protect
Writing 0x96 removes the write
protection of the MISC regis-
ters (0x5326–0x532a).
Writing another value set the
write protection.
0x0 R/W
IRAM Size
Select Register
(MISC_IRAMSZ)
0x5326
(16 bits)
D15–9 –
reserved
–
0 when being read.
D8
DBADR
Debug base address select
1 0x0
0 0xfffc00
0
R/W
D7
–
reserved
–
0 when being read.
D6–4 IRAMACTSZ
[2:0]
IRAM actual size
0x3 (= 2KB)
0x3
R
D3
–
reserved
–
0 when being read.
D2–0 IRAMSZ[2:0] IRAM size select
IRAMSZ[2:0]
Size
0x3 R/W
0x5
0x4
0x3
Other
512B
1KB
2KB
reserved
Vector Table
Address Low
Register
(MISC_TTBRL)
0x5328
(16 bits)
D15–8 TTBR[15:8] Vector table base address A[15:8]
0x0–0xff
0x80 R/W
D7–0 TTBR[7:0]
Vector table base address A[7:0]
(fixed at 0)
0x0
R
Vector Table
Address High
Register
(MISC_TTBRH)
0x532a
(16 bits)
D15–8 –
reserved
–
0 when being read.
D7–0 TTBR[23:16] Vector table base address
A[23:16]
0x0–0xff
0x0 R/W
PSR Register
(MISC_PSR)
0x532c
(16 bits)
D15–8 –
reserved
–
0 when being read.
D7–5 PSRIL[2:0] PSR interrupt level (IL) bits
0x0 to 0x7
0x0
R
D4
PSRIE
PSR interrupt enable (IE) bit
1 1 (enable)
0 0 (disable)
0
R
D3
PSRC
PSR carry (C) flag
1 1 (set)
0 0 (cleared)
0
R
D2
PSRV
PSR overflow (V) flag
1 1 (set)
0 0 (cleared)
0
R
D1
PSRZ
PSR zero (Z) flag
1 1 (set)
0 0 (cleared)
0
R
D0
PSRN
PSR negative (N) flag
1 1 (set)
0 0 (cleared)
0
R
0x5068, 0x5400–0x540c
16-bit PWM Timer Ch.0
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
T16A Clock
Control Register
Ch.0
(T16A_CLK0)
0x5068
(8 bits)
D7–4 T16ACLKD
[3:0]
Clock division ratio select
T16ACLKD[3:0]
Division ratio
0x0 R/W F256: Regulated 256
Hz clock
OSC3A
or
OSC3B
OSC1
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
–
1/16384
1/8192
1/4096
1/2048
1/1024
1/512
1/256
1/128
1/64
1/32
1/16
1/8
1/4
1/2
1/1
–
F256
1/256
1/128
1/64
1/32
1/16
1/8
1/4
1/2
1/1
D3–2 T16ACLK
SRC[1:0]
Clock source select
T16ACLKSRC
[1:0]
Clock source
0x0 R/W
0x3
0x2
0x1
0x0
External clock
OSC3A
OSC1
OSC3B
D1
–
reserved
–
0 when being read.
D0
T16ACLKE Count clock enable
1 Enable
0 Disable
0
R/W
T16A Counter
Ch.0 Control
Register
(T16A_CTL0)
0x5400
(16 bits)
D15–7 –
reserved
–
0 when being read.
D6
HCM
Half clock mode enable
1 Enable
0 Disable
0
R/W
D5–4 –
reserved
–
0 when being read.
D3
CBUFEN
Compare buffer enable
1 Enable
0 Disable
0
R/W
D2
TRMD
Count mode select
1 One-shot
0 Repeat
0
R/W
D1
PRESET
Counter reset
1 Reset
0 Ignored
0
W 0 when being read.
D0
PRUN
Counter run/stop control
1 Run
0 Stop
0
R/W