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| 型号： | S29JL032J70TFI213 |
| 厂商： | SPANSION LLC |
| 元件分类： | PROM |
| 英文描述： | 2M X 16 FLASH 3V PROM, 70 ns, PDSO48 |
| 封装： | LEAD FREE, MO-142(D)DD, TSOP-48 |
| 文件页数： | 29/63页 |
| 文件大小： | 1618K |
| 代理商： | S29JL032J70TFI213 |
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August 24, 2011 S29JL032J_00_05
S29JL032J
35
Data
Sheet
10.6
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical erase. The system is not required to provide any
controls or timings during these operations. Table 10.1 on page 38 shows the address and data requirements
for the chip erase command sequence.
When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no
longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/
BY#. Refer to Write Operation Status on page 39 for information on these status bits.
Any commands written during the chip erase operation are ignored. However, note that a hardware reset
immediately terminates the erase operation. If that occurs, the chip erase command sequence should be
reinitiated once that bank has returned to reading array data, to ensure data integrity. Note that the Secured
Silicon Region, autoselect, and CFI functions are unavailable when an erase operation is in progress.
Figure 10.2 on page 36 illustrates the algorithm for the erase operation. Refer to Erase and Program
Operations on page 51 for parameters, and Figure 17.7 on page 53 for timing diagrams.
10.7
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed
by the address of the sector to be erased, and the sector erase command. Table 10.1 on page 38 shows the
address and data requirements for the sector erase command sequence.
The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm
automatically programs and verifies the entire sector for an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 80 s occurs. During the time-out period,
additional sector addresses and sector erase commands may be written. However, these additional erase
commands are only one bus cycle long and should be identical to the sixth cycle of the standard erase
command explained above. Loading the sector erase buffer may be done in any sequence, and the number
of sectors may be from one sector to all sectors. The time between these additional cycles must be less than
80 s, otherwise erasure may begin. Any sector erase address and command following the exceeded time-
out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to
ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is
written. If any command other than 30h, B0h, F0h is input during the time-out period, the normal
operation will not be guaranteed. The system must rewrite the command sequence and any additional
addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out (See DQ3: Sector Erase
Timer on page 43.). The time-out begins from the rising edge of the final WE# or CE# pulse (first rising edge)
in the command sequence.
When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are
no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data
from the non-erasing bank. The system can determine the status of the erase operation by reading DQ7,
DQ6, DQ2, or RY/BY# in the erasing bank. Refer to Write Operation Status on page 39 for information on
these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands
are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs,
the sector erase command sequence should be reinitiated once that bank has returned to reading array data,
to ensure data integrity. Note that the Secured Silicon Region, autoselect, and CFI functions are unavailable
when an erase operation is in progress.
Figure 10.2 on page 36 illustrates the algorithm for the erase operation. Refer to Erase and Program
Operations on page 51 for parameters, and Figure 17.7 on page 53 for timing diagrams.
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| S29JL032J70TFI220 | 功能描述:闪存 32MB 闪存 3.0V 70ns Parallel NOR 闪存 RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| S29JL032J70TFI310 | 功能描述:闪存 32MB 闪存 3.0V 70ns Parallel NOR 闪存 RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| S29JL032J70TFI313 | 制造商:Spansion 功能描述: |
| S29JL032J70TFI320 | 功能描述:闪存 32Mb 3V 70ns Parallel NOR 闪存 RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| S29JL032J70TFI323 | 功能描述:闪存 32M, 3V, 70ns Parallel NOR 闪存 RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
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