- 您现在的位置：买卖IC网 > PDF目录192300 > S29JL032J70TFI213 (SPANSION LLC) 2M X 16 FLASH 3V PROM, 70 ns, PDSO48 PDF资料下载
参数资料
| 型号： | S29JL032J70TFI213 |
| 厂商： | SPANSION LLC |
| 元件分类： | PROM |
| 英文描述： | 2M X 16 FLASH 3V PROM, 70 ns, PDSO48 |
| 封装： | LEAD FREE, MO-142(D)DD, TSOP-48 |
| 文件页数： | 37/63页 |
| 文件大小： | 1618K |
| 代理商： | S29JL032J70TFI213 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页当前第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页
42
S29JL032J
S29JL032J_00_05 August 24, 2011
Data
She e t
11.4
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that
is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is
valid after the rising edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure.
(The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the
sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is
actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus,
both status bits are required for sector and mode information. Refer to Table 11.1 on page 43 to compare
outputs for DQ2 and DQ6.
Figure 11.2 on page 41 shows the toggle bit algorithm in flowchart form, and DQ2: Toggle Bit II on page 42
explains the algorithm. See also DQ6: Toggle Bit I on page 40. Figure 17.10 on page 54 shows the toggle bit
timing diagram. Figure 17.11 on page 55 shows the differences between DQ2 and DQ6 in graphical form.
11.5
Reading Toggle Bits DQ6/DQ2
Refer to Figure 11.2 on page 41 for the following discussion. Whenever the system initially begins reading
toggle bit status, it must read DQ15–DQ0 (or DQ7–DQ0 for x8-only device) at least twice in a row to
determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle
bit after the first read. After the second read, the system would compare the new value of the toggle bit with
the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system
can read array data on DQ15–DQ0 (or DQ7–DQ0 for x8-only device) on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as
DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or
erase operation. If it is still toggling, the device did not completed the operation successfully, and the system
must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algorithm when it returns to
determine the status of the operation (top of Figure 11.2 on page 41).
11.6
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully
completed.
The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously
programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.” The
RDY/BSY# pin will be in the BUSY state under this condition.
Under both these conditions, the system must write the reset command to return to the read mode (or to the
erase-suspend-read mode if a bank was previously in the erase-suspend-program mode).
相关PDF资料 |
PDF描述 |
|---|---|
| S29PL032J65BFI150 | 2M X 16 FLASH 3V PROM, 65 ns, PBGA56 |
| S29PL127J70BFI000 | 8M X 16 FLASH 3V PROM, 70 ns, PBGA80 |
| S29XS064R0PBHW010 | 4M X 16 FLASH 1.8V PROM, 80 ns, PBGA44 |
| S2C3R-1-12-H | 4000 MHz - 12000 MHz RF/MICROWAVE SGL POLE DOUBLE THROW SWITCH, 2 dB INSERTION LOSS |
| S2C5R-1-12-RC | 4000 MHz - 18000 MHz RF/MICROWAVE SGL POLE DOUBLE THROW SWITCH, 2.8 dB INSERTION LOSS |
相关代理商/技术参数 |
参数描述 |
|---|---|
| S29JL032J70TFI220 | 功能描述:闪存 32MB 闪存 3.0V 70ns Parallel NOR 闪存 RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| S29JL032J70TFI310 | 功能描述:闪存 32MB 闪存 3.0V 70ns Parallel NOR 闪存 RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| S29JL032J70TFI313 | 制造商:Spansion 功能描述: |
| S29JL032J70TFI320 | 功能描述:闪存 32Mb 3V 70ns Parallel NOR 闪存 RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| S29JL032J70TFI323 | 功能描述:闪存 32M, 3V, 70ns Parallel NOR 闪存 RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
发布紧急采购，3分钟左右您将得到回复。