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参数资料
| 型号： | SSTUP32866EC/S |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 锁存器 |
| 英文描述： | 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96 |
| 封装： | 13.50 X 5.50 MM, 1.05 MM HEIGHT, LEAD FREE, PLASTIC, SOT-536-1, LFBGA-96 |
| 文件页数： | 11/31页 |
| 文件大小： | 538K |
| 代理商： | SSTUP32866EC/S |
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SSTUP32866_2
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 14 September 2006
19 of 31
Philips Semiconductors
SSTUP32866
1.8 V DDR2-667/800 programmable registered buffer with parity
11. Test information
11.1 Parameter measurement information for data output load circuit
VDD = 1.8 V ± 0.1 V.
All input pulses are supplied by generators having the following characteristics:
PRR
≤ 10 MHz; Z
0 =50 ; input slew rate = 1 V/ns ± 20 %, unless otherwise specied.
The outputs are measured one at a time with one transition per measurement.
(1) CL includes probe and jig capacitance.
Fig 10. Load circuit, data output measurements
(1) IDD tested with clock and data inputs held at VDD or GND, and IO = 0 mA.
Fig 11. Voltage and current waveforms; inputs active and inactive times
VID = 600 mV.
VIH =Vref + 250 mV (AC voltage levels) for differential inputs. VIH =VDD for LVCMOS inputs.
VIL =Vref 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 12. Voltage waveforms; pulse duration
RL = 100
RL = 1000
VDD
50
CK inputs
CK
OUT
DUT
test point
002aaa371
test point
delay = 350 ps
Zo = 50
RL = 1000
CL = 30 pF(1)
LVCMOS
RESET
10 %
IDD(1)
tINACT
VDD
0.5VDD
tACT
90 %
0 V
002aaa372
0.5VDD
VICR
VIH
VIL
input
tW
VID
002aaa373
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