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参数资料
| 型号： | SSTUP32866EC/S |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 锁存器 |
| 英文描述： | 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96 |
| 封装： | 13.50 X 5.50 MM, 1.05 MM HEIGHT, LEAD FREE, PLASTIC, SOT-536-1, LFBGA-96 |
| 文件页数： | 31/31页 |
| 文件大小： | 538K |
| 代理商： | SSTUP32866EC/S |
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SSTUP32866_2
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 14 September 2006
9 of 31
Philips Semiconductors
SSTUP32866
1.8 V DDR2-667/800 programmable registered buffer with parity
When used in pairs, the C0 input of the rst register is tied LOW and the C0 input of the
second register is tied HIGH. The C1 input of both registers are tied HIGH. Parity, which
arrives one cycle after the data input to which it applies, is checked on the PAR_IN input of
the rst device. The PPO and QERR signals are produced on the second device three
clock cycles after the corresponding data inputs. The PPO output of the rst register is
cascaded to the PAR_IN of the second register. The QERR output of the rst register is
left oating and the valid error information is latched on the QERR output of the second
register.
If an error occurs and the QERR output is driven LOW, it stays latched LOW for two clock
cycles or until RESET is driven LOW. The DIMM-dependent signals (DCKE, DCS, DODT,
and CSR) are not included in the parity check computation.
The device supports low-power standby operation. When RESET is LOW, the differential
input receivers are disabled, and undriven (oating) data, clock and reference voltage
(VREF) inputs are allowed. In addition, when RESET is LOW all registers are reset, and
all outputs are forced LOW. The LVCMOS RESET input must always be held at a valid
logic HIGH or LOW level.
The device also supports low-power active operation by monitoring both system chip
select (DCS and CSR) inputs and will gate the Qn and PPO outputs from changing states
when both DCS and CSR inputs are HIGH. If either DCS or CSR input is LOW, the Qn
and PPO outputs will function normally. The RESET input has priority over the DCS and
CSR control and when driven LOW will force the Qn and PPO outputs LOW, and the
QERR output HIGH. If the DCS control functionality is not desired, then the CSR input can
be hard-wired to ground, in which case, the setup time requirement for DCS would be the
same as for the other Dn data inputs. To control the low-power mode with DCS only, then
the CSR input should be pulled up to VDD through a pull-up resistor.
To ensure dened outputs from the register before a stable clock has been supplied,
RESET must be held in the LOW state during power-up.
In the DDR2 RDIMM application, RESET is specied to be completely asynchronous with
respect to CK and CK. Therefore, no timing relationship can be guaranteed between the
two. When entering reset, the register will be cleared and the Qn outputs will be driven
LOW quickly, relative to the time to disable the differential input receivers. However, when
coming out of reset, the register will become active quickly, relative to the time to enable
the differential input receivers. As long as the data inputs are LOW, and the clock is stable
during the time from the LOW-to-HIGH transition of RESET until the input receivers are
fully enabled, the design of the SSTUP32866 must ensure that the outputs will remain
LOW, thus ensuring no glitches on the output.
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