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参数资料
| 型号： | SSTUP32866EC/S |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 锁存器 |
| 英文描述： | 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96 |
| 封装： | 13.50 X 5.50 MM, 1.05 MM HEIGHT, LEAD FREE, PLASTIC, SOT-536-1, LFBGA-96 |
| 文件页数： | 7/31页 |
| 文件大小： | 538K |
| 代理商： | SSTUP32866EC/S |
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SSTUP32866_2
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 14 September 2006
15 of 31
Philips Semiconductors
SSTUP32866
1.8 V DDR2-667/800 programmable registered buffer with parity
[1]
Includes 350 ps of test load transmission line delay.
[2]
This parameter is not necessarily production tested.
Table 12.
Switching characteristics (800 mode, SELAB = LOW)
At recommended operating conditions (see Table 8), unless otherwise specied. See Section 11.1.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fmax
maximum input clock frequency
450
-
MHz
tPDM
peak propagation delay
single bit switching;
from CK
↑ and CK↓ to Qn
[1] 1.1
-
1.5
ns
tPD
propagation delay
from CK
↑ and CK↓ to PPO
0.5
-
1.7
ns
tLH
LOW-to-HIGH delay
from CK
↑ and CK↓ to QERR
1.2
-
3
ns
tHL
HIGH-to-LOW delay
from CK
↑ and CK↓ to QERR
1
-
2.4
ns
tPDMSS
simultaneous switching peak
propagation delay
from CK
↑ and CK↓ to Qn
[1][2] -
-
1.6
ns
tPHL
HIGH-to-LOW propagation delay
from RESET
↓ to Qn↓
--3
ns
from RESET
↓ to PPO↓
--3
ns
tPLH
LOW-to-HIGH propagation delay
from RESET
↓ to QERR↑
--3
ns
Table 13.
Data output edge rates
At recommended operating conditions (see Table 8), unless otherwise specied. See Section 11.2.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
dV/dt_r
rising edge slew rate
from 20 % to 80 %
1
-
4
V/ns
dV/dt_f
falling edge slew rate
from 80 % to 20 %
1
-
4
V/ns
dV/dt_
absolute difference between dV/dt_r
and dV/dt_f
from 20 % or 80 %
to 80 % or 20 %
-
1
V/ns
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