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参数资料
| 型号： | SSTUP32866EC/S |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 锁存器 |
| 英文描述： | 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96 |
| 封装： | 13.50 X 5.50 MM, 1.05 MM HEIGHT, LEAD FREE, PLASTIC, SOT-536-1, LFBGA-96 |
| 文件页数： | 30/31页 |
| 文件大小： | 538K |
| 代理商： | SSTUP32866EC/S |
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SSTUP32866_2
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 14 September 2006
8 of 31
Philips Semiconductors
SSTUP32866
1.8 V DDR2-667/800 programmable registered buffer with parity
[1]
Data inputs = D2, D3, D5, D6, D8 to D25 when C0 = 0 and C1 = 0.
Data inputs = D2, D3, D5, D6, D8 to D14 when C0 = 0 and C1 = 1.
Data inputs = D1 to D6, D8 to D10, D12, D13 when C0 = 1 and C1 = 1.
[2]
[3]
Data outputs = Q2, Q3, Q5, Q6, Q8 to Q25 when C0 = 0 and C1 = 0.
Data outputs = Q2, Q3, Q5, Q6, Q8 to Q14 when C0 = 0 and C1 = 1.
Data outputs = Q1 to Q6, Q8 to Q10, Q12, Q13 when C0 = 1 and C1 = 1.
7.
Functional description
The SSTUP32866 is a 25-bit 1 : 1 or 14-bit 1 : 2 congurable registered buffer with parity,
designed for 1.7 V to 2.0 V VDD operation. Additionally, the SSTUP32866 can be
programmed to deliver either normal or high output drive, and either 600 MT/s or
800 MT/s speeds.
Two programming pins, SELAB and SELDR, allow the user to respectively select speed
and drive strength options by tying these pins either LOW or HIGH on the DIMM. The truth
table for these options is shown in Table 6.
All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The
control and reset (RESET) inputs are LVCMOS. All data outputs are 1.8 V CMOS drivers
that have been optimized to drive the DDR2 DIMM load, and meet SSTL_18
specications. The error (QERR) output is 1.8 V open-drain driver.
The SSTUP32866 operates from a differential clock (CK and CK). Data are registered at
the crossing of CK going HIGH, and CK going LOW.
The C0 input controls the pinout conguration for the 1 : 2 pinout from A conguration
(when LOW) to B conguration (when HIGH). The C1 input controls the pinout
conguration from 25-bit 1 : 1 (when LOW) to 14-bit 1 : 2 (when HIGH).
The SSTUP32866 accepts a parity bit from the memory controller on its parity bit
(PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs
and indicates whether a parity error has occurred on its open-drain QERR pin
(active LOW). The convention is even parity, that is, valid parity is dened as an even
number of ones across the DIMM-independent data inputs combined with the parity input
bit.
When used as a single device, the C0 and C1 inputs are tied LOW. In this conguration,
parity is checked on the PAR_IN input which arrives one cycle after the input data to which
it applies. The Partial-Parity-Out (PPO) and QERR signals are produced three cycles after
the corresponding data inputs.
QCKE, QCKEA,
QCKEB
1.8 V CMOS
output
Data output that will not be suspended by
the DCS and CSR control.
QERR
D2
open-drain
output
Output error bit (active LOW). Generated
one clock cycle after the corresponding
data output
DNU
-
Do not use. Inputs are in
standby-equivalent mode and outputs
are driven LOW.
Table 3.
Pin description …continued
Symbol
Pin
Type
Description
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