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参数资料
| 型号： | SSTUP32866EC/S |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 锁存器 |
| 英文描述： | 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96 |
| 封装： | 13.50 X 5.50 MM, 1.05 MM HEIGHT, LEAD FREE, PLASTIC, SOT-536-1, LFBGA-96 |
| 文件页数： | 29/31页 |
| 文件大小： | 538K |
| 代理商： | SSTUP32866EC/S |
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SSTUP32866_2
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 14 September 2006
7 of 31
Philips Semiconductors
SSTUP32866
1.8 V DDR2-667/800 programmable registered buffer with parity
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
Type
Description
GND
B3, B4, D3, D4,
F3, F4, H3, H4,
K3, K4, M3, M4,
P3, P4
ground input
ground
VDD
A4, C3, C4, E3,
E4, G3, G4, J3,
J4, L3, L4, N3,
N4, R3, R4, T4
1.8 V nominal
power supply voltage
VREF
A3, T3
0.9 V nominal
input reference voltage
CK
H1
differential input
positive master clock input
CK
J1
differential input
negative master clock input
C0
G6
LVCMOS inputs
Conguration control inputs; Register A
or Register B and 1 : 1 mode or
1 : 2 mode select.
C1
G5
SELDR
J6
LVCMOS input
Selects output drive strength: HIGH for
normal drive, LOW for high drive. This pin
will default HIGH if left open-circuit
(built-in weak pull-up resistor).
SELAB
J5
LVCMOS input
Selects speed grade: HIGH for
DDR2-667, LOW for DDR2-800. This pin
will default HIGH if left open-circuit
(built-in weak pull-up resistor).
RESET
G2
LVCMOS input
Asynchronous reset input (active LOW).
Resets registers and disables VREF data
and clock.
CSR
J2
SSTL_18 input
Chip select inputs (active LOW). Disables
D1 to D25[1] outputs switching when both
inputs are HIGH.
DCS
H2
D1 to D25
SSTL_18 input
Data input. Clocked in on the crossing of
the rising edge of CK and the falling edge
of CK.
DODT
SSTL_18 input
The outputs of this register bit will not be
suspended by the DCS and CSR control.
DCKE
SSTL_18 input
The outputs of this register bit will not be
suspended by the DCS and CSR control.
PAR_IN
G1
SSTL_18 input
Parity input. Arrives one clock cycle after
the corresponding data input.
Q1 to Q25,
Q2A to Q14A,
Q1B to Q14B
1.8 V CMOS
outputs
Data outputs that are suspended by the
DCS and CSR control[3].
PPO
A2
1.8 V CMOS
output
Partial parity out. Indicates odd parity of
inputs D1 to D25[1].
QCS, QCSA,
QCSB
1.8 V CMOS
output
Data output that will not be suspended by
the DCS and CSR control.
QODT, QODTA,
QODTB
1.8 V CMOS
output
Data output that will not be suspended by
the DCS and CSR control.
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