参数资料
型号: SSTUP32866EC/S
厂商: NXP SEMICONDUCTORS
元件分类: 锁存器
英文描述: 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
封装: 13.50 X 5.50 MM, 1.05 MM HEIGHT, LEAD FREE, PLASTIC, SOT-536-1, LFBGA-96
文件页数: 5/31页
文件大小: 538K
代理商: SSTUP32866EC/S
SSTUP32866_2
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 14 September 2006
13 of 31
Philips Semiconductors
SSTUP32866
1.8 V DDR2-667/800 programmable registered buffer with parity
10. Characteristics
[1]
Instantaneous is dened as within < 2 ns following the output data transition edge.
Table 9.
Characteristics
At recommended operating conditions (see Table 8); unless otherwise specied.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOH
HIGH-level output voltage
IOH = 6 mA; VDD = 1.7 V
1.2
-
V
VOL
LOW-level output voltage
IOL = 6 mA; VDD = 1.7 V
-
0.5
V
II
input current
all inputs; VI =VDD or GND;
VDD = 2.0 V
--
±5
A
IDD
supply current
static Standby mode; RESET = GND;
IO = 0 mA; VDD = 2.0 V
-
100
A
static Operating mode;
RESET = VDD; IO = 0 mA;
VDD = 2.0 V; VI =VIH(AC) or VIL(AC)
-
40
mA
IDDD
dynamic operating current per MHz
clock only; RESET = VDD;
VI =VIH(AC) or VIL(AC); CK and CK
switching at 50 % duty cycle;
IO = 0 mA; VDD = 1.8 V
-16
-
A
per each data input, 1 : 1 mode;
RESET = VDD; VI =VIH(AC) or VIL(AC);
CK and CK switching at 50 % duty
cycle; one data input switching at half
clock frequency, 50 % duty cycle;
IO = 0 mA; VDD = 1.8 V
-11
-
A
per each data input, 1 : 2 mode;
RESET = VDD; VI =VIH(AC) or VIL(AC);
CK and CK switching at 50 % duty
cycle; one data input switching at half
clock frequency, 50 % duty cycle;
IO = 0 mA; VDD = 1.8 V
-19
-
A
Ci
input capacitance
data and CSR inputs;
VI =Vref ± 250 mV; VDD = 1.8 V
2.5
-
3.5
pF
CK and CK inputs; VICR = 0.9 V;
Vi(p-p) = 600 mV; VDD = 1.8 V
2-
3pF
RESET input; VI =VDD or GND;
VDD = 1.8 V
3-
4pF
Zo
output impedance
normal drive; instantaneous
[1] -15
-
normal drive; steady-state
-
53
-
high drive; instantaneous
-
high drive; steady-state
-
53
-
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