参数资料
型号: ST40RA200XH6E
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 200 MHz, RISC PROCESSOR, PBGA372
封装: 27 X 27 MM, 2.33 MM HEIGHT, PLASTIC, BGA-372
文件页数: 46/94页
文件大小: 2144K
代理商: ST40RA200XH6E
50/92
ST40RA
6 Clock generation
6.4.1
Programming the PLL output frequency
The three dividers used within the PLL are referred to as M (predivider), N (feedback divider) and P
(postdivider) for brevity. Note that there is a divide-by-2 fixed prescaler before the feedback divider.
The binary values applied to the programmable dividers, and the frequency of CLOCKIN controls
the output frequency of the PLL macrocell:
where the values of M, N and P must satisfy the following constraints:
Divider limits:
,
Phase comparator limits:
,
VCO limit:
,
M divider limit:
.
For example, if 300 MHz from an input clock of 33 MHz is to be generated, the values of M, N and
P are worked out as below.
1
The phase comparator must operate between 1 MHz and 2 MHz, so choose M = 22 (for
1.5 MHz operation).
2
The VCO needs to run between 200 MHz and 622 MHz. It could be run at 300 MHz directly
(which takes a little less current), or at 600 MHz then divide by 2 to ensure an exact 50% duty
cycle. In this example 600 MHz is chosen so N = 200.
3
The postdivider then needs to be a divide by 2. This is programmed in powers of 2, so P = 1.
The P divider changes value without glitching of the output clock.
6.4.2
Changing clock frequency
The clock frequencies are changed in two ways.
Change the core PLL frequencies.
The PLL must be stopped, the control register reconfigured with the new settings, and the PLL
restarted at the new frequency.
Change the frequency division ratio of the clock domains.
The control registers are changed dynamically and the new frequencies are effective
immediately.
6.4.3
Changing the core PLL frequencies
This procedure applies to either CLOCKGENA or CLOCKGENB and to PLL1 or PLL2.
1
Stop the PLL. The CLOCKGENA.PLL1CR2.STBPLLENSEL register selects whether the PLL
is enabled by the CLOCKGENA.PLL1CR2.STBPLLEN or the CPG.FRQCR.PLL1EN register.
2
Reconfigure the PLL. Set the CLOCKGENA.PLL1CR1 register to one of the supported
configurations on the datasheet.
3
Restart the PLL, following the procedure described in the ST40 System Architecture Volume 1:
System.
F clockout
()
2N
×
M2P
×
------------------
F clockin
()
×
=
1
M
255 1
N
255 0
P
5
≤≤
,
≤≤
,
≤≤
1MHz
F clockin
()
M
-----------------------------
2MHz
≤≤
200MHz
2N
×
M
-------------
F clockin
()
×
622MHz
≤≤
F clockin
() 200MHz
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