参数资料
型号: ST40RA200XH6E
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 200 MHz, RISC PROCESSOR, PBGA372
封装: 27 X 27 MM, 2.33 MM HEIGHT, PLASTIC, BGA-372
文件页数: 89/94页
文件大小: 2144K
代理商: ST40RA200XH6E
A Interconnect architecture
ST40RA
A.2.1
LMI1 arbiter
0x230
EMI_LATENCY_GPDMA
Defines priority and latency value for GPDMA initiator in the EMI arbiter,
0x310
LATENCY_PCI_ENABLE
Enables or disables initiators latency counters, see PCI arbiter on page 12
0x318
PCI_CPU_PRI
Defines priority for the CPU in the PCI arbiter, see PCI arbiter on page 12
0x320
PCI_LATENCY_PCI
Defines priority and latency value for PCI initiator in the PCI arbiter, see PCI
0x328
PCI_LATENCY_EMPI
Defines priority and latency value for EMPI initiator in the PCI arbiter, see
0x330
PCI_LATENCY_GPDMA
Defines priority and latency value for GPDMA initiator in the PCI arbiter, see
0x410
LATENCY_PER_ENABLE
Enables or disables initiators latency counters, see Peripheral arbiter on
0x418
PER_CPU_PRI
Defines priority for the CPU in the peripheral arbiter, see Peripheral arbiter
0x420
PER_LATENCY_PCI
Defines priority and latency value for PCI initiator in the peripheral arbiter,
0x428
PER_LATENCY_EMPI
Defines priority and latency value for EMPI initiator in the peripheral arbiter,
0x430
PER_LATENCY_GPDMA
Defines priority and latency value for GPDMA initiator in the peripheral
LATENCY_LMI1_ENABLE
LMI1 arbiter: enable latency counters
0x010
0
Reserved
Reset: Always 0
1
ENABLE_1
Enable latency check for node 2
Reset: 0
RW
[31:2]
Reserved
Reset: Always 0
LMI1_CPU_PRI
LMI1 arbiter: CPU priority
0x018
[3:0]
CPU_PRIORITY
Defines priority for CPU
Reset: 0x1
RW
[31:4]
Reserved
LATENCY_LMI1_VALUE
LMI1 arbiter: node 2 intitiator priority and latency
0x020
[3:0]
NODE2_PRIORITY
Defines priority for node 2 initiators
Reset: 0x0
RW
[15:4]
Reserved
Table 1: Interconnect register summary
Address
offset
Name
Function
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