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参数资料
| 型号： | ST40RA200XH6E |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA372 |
| 封装： | 27 X 27 MM, 2.33 MM HEIGHT, PLASTIC, BGA-372 |
| 文件页数： | 47/94页 |
| 文件大小： | 2144K |
| 代理商： | ST40RA200XH6E |
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6 Clock generation
ST40RA
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6.4.4
Changing the frequency division ratio
The frequency division ratio is selected by changing the CPG.FRQCR register for PLL1 or the
CLOCKGENA.PLL2_MUXCR register for PLL2. This change is immediately effective.
6.5
Power management
The power management unit (PMU) is responsible for clock startup and shutdown for each of the
on-chip modules. Power is conserved by powering down those modules which are not in use, or
even the CPU itself.
The PMU is operated using three banks of registers as follows:
● CPG: controls the power-down mode of the CPU and the power-down states of the legacy
on-chip peripherals,
● CLOCKGENA and CLOCKGENB: control the power-down states of the other on-chip peripherals.
6.5.1
CPU low-power modes
The CPU can be put into sleep or standby modes. In sleep mode the CPU is halted while the
on-chip peripherals continue to operate. In standby mode all the on-chip peripherals are stopped
along with the CPU. In addition, the on-chip peripherals can be independently stopped.
Power down is initiated with the sleep instruction and the power down mode is selected with bit 7 of
the CPG.STBCR register. If the bit is set, the CPU enters standby mode on the next sleep
instruction, and if unset it enters sleep mode.
6.5.2
Module low-power modes
Modules are powered down in two ways, depending on whether the module is a ST40 legacy
peripheral (controlled by the CPG register bank) or a ST40RA peripheral (controlled by the
CLOCKGEN register banks).
A module controlled by the CPG register bank has its clock stopped when the corresponding bit in
the CPG.STBCR or CPG.STBCR2 register is set. The clock is started again when the bit is cleared.
To request the power down of a module controlled by the CLOCKGENA or CLOCKGENB register
bank, 1 is written to the corresponding bit in the STBREQCR_SET register. When the module has
completed its power down sequence and its clock has been stopped, the corresponding bit in the
STBACKCR register is set. To restart the module, 1 is written to the corresponding bit in the
STBREQCR_CLR register.
Note:
The modules governed by the CLOCKGENB register bank do not support hardware-only power down
and require software interaction to maintain data coherency before making a request to stop the
module clock.
6.6
Clock generation registers
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