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Obsolete
Product(s)
- Obsolete
Product(s)
Register and memory map
ST72324B-Auto
Legend: x = undefined, R/W = read/write
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
Timer B
TBCR2
TBCR1
TBCSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
TBCLR
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR
Timer B control register 2
Timer B control register 1
Timer B control/status register
Timer B input capture 1 high register
Timer B input capture 1 low register
Timer B output compare 1 high register
Timer B output compare 1 low register
Timer B counter high register
Timer B counter low register
Timer B alternate counter high register
Timer B alternate counter low register
Timer B input capture 2 high register
Timer B input capture 2 low register
Timer B output compare 2 high register
Timer B output compare 2 low register
00h
xxxx x0xxb
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
80h
00h
R/W
Read only
R/W
Read only
R/W
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
SCI
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCIERPR
SCIETPR
SCI status register
SCI data register
SCI baud rate register
SCI control register 1
SCI control register 2
SCI extended receive prescaler register
Reserved area
SCI extended transmit prescaler register
C0h
xxh
00h
x000 0000b
00h
---
00h
Read only
R/W
0058h to
006Fh
Reserved area (24 bytes)
0070h
0071h
0072h
ADC
ADCCSR
ADCDRH
ADCDRL
Control/status register
Data high register
Data low register
00h
R/W
Read only
0073h
007Fh
Reserved area (13 bytes)
1.
The bits associated with unavailable pins must always keep their reset value.
2.
The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the
I/O pins are returned instead of the DR register contents.
Table 3.
Hardware register map (continued)
Address
Block
Register label
Register name
Reset status
Remarks