Obsolete
Product(s)
- Obsolete
Product(s)
On-chip peripherals
ST72324B-Auto
SCI Control Register 1 (SCICR1)
0PE
Parity Error
This bit is set by hardware when a parity error occurs in receiver mode. It is cleared
by a software sequence (a read to the status register followed by an access to the
SCIDR data register). An interrupt is generated if PIE = 1 in the SCICR1 register.
0: No parity error
1: Parity error
SCICR1
Reset value: x000 0000 (x0h)
7
654
32
10
R8
T8
SCID
M
WAKE
PCE
PS
PIE
R/W
Table 63.
SCICR1 register description
Bit
Name
Function
7R8
Receive data bit 8
This bit is used to store the 9th bit of the received word when M = 1.
6T8
Transmit data bit 8
This bit is used to store the 9th bit of the transmitted word when M = 1.
5SCID
Disabled for low power consumption
When this bit is set the SCI prescalers and outputs are stopped and the end of the
current byte transfer in order to reduce power consumption.This bit is set and
cleared by software.
0: SCI enabled
1: SCI prescaler and outputs disabled
4M
Word length
This bit determines the word length. It is set or cleared by software.
0: 1 Start bit, 8 data bits, 1 Stop bit
1: 1 Start bit, 9 data bits, 1 Stop bit
Note: The M bit must not be modified during a data transfer (both transmission and
reception).
3WAKE
Wake-Up method
This bit determines the SCI Wake-Up method, it is set or cleared by software.
0: Idle line
1: Address mark
2PCE
Parity Control Enable
This bit selects the hardware parity control (generation and detection). When the
parity control is enabled, the computed parity is inserted at the MSB position (9th bit
if M = 1; 8th bit if M = 0) and parity is checked on the received data. This bit is set
and cleared by software. Once it is set, PCE is active after the current byte (in
reception and in transmission).
0: Parity control disabled
1: Parity control enabled
Table 62.
SCISR register description (continued)
Bit
Name
Function