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Supply, reset and clock management
ST72324B-Auto
6.4
Reset sequence manager (RSM)
The reset sequence manager includes three reset sources as shown in
Figure 12:●
External reset source pulse
●
Internal LVD reset
●
Internal Watchdog reset
These sources act on the RESET pin and it is always kept low during the delay phase.
The reset service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory
map.
The basic reset sequence consists of three phases as shown in
Figure 11:●
Active Phase depending on the reset source
●
256 or 4096 CPU clock cycle delay (selected by option byte)
●
Reset vector fetch
Caution:
When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is
not programmed. For this reason, it is recommended to keep the RESET pin in low state
until programming mode is entered, in order to avoid unwanted behavior.
The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilize and ensures that
recovery has taken place from the reset state. The shorter or longer clock cycle delay
should be selected by option byte to correspond to the stabilization time of the external
oscillator used in the application.
The reset vector fetch phase duration is two clock cycles.
Figure 11.
Reset sequence phases
6.4.1
Asynchronous external RESET pin
The RESET pin is both an input and an open-drain output with integrated RON weak pull-up
resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It
section for more details.
A reset signal originating from an external source must have a duration of at least th(RSTL)in
in order to be recognized (see
Figure 13). This detection is asynchronous and therefore the
MCU can enter reset state even in Halt mode.
RESET
ACTIVE PHASE
INTERNAL RESET
256 or 4096 CLOCK CYCLES
FETCH
VECTOR