Obsolete
Product(s)
- Obsolete
Product(s)
ST72324B-Auto
On-chip peripherals
Clock deviation causes
The causes which contribute to the total deviation are:
–DTRA: Deviation due to transmitter error (local oscillator error of the transmitter or
the transmitter is transmitting at a different baud rate).
–DQUANT: Error due to the baud rate quantization of the receiver.
–DREC: Deviation of the local oscillator of the receiver: This deviation can occur
during the reception of one complete SCI message assuming that the deviation
has been compensated at the beginning of the message.
–DTCL: Deviation due to the transmission line (generally due to the transceivers)
All the deviations of the system should be added and compared to the SCI clock tolerance:
DTRA + DQUANT + DREC + DTCL < 3.75%
Noise error causes
Start bit
The Noise Flag (NF) is set during start bit reception if one of the following conditions occurs:
1.
A valid falling edge is not detected. A falling edge is considered to be valid if the three
consecutive samples before the falling edge occurs are detected as ‘1’ and, after the
falling edge occurs, during the sampling of the 16 samples, if one of the samples
numbered 3, 5 or 7 is detected as a ‘1’.
2.
During sampling of the 16 samples, if one of the samples numbered 8, 9 or 10 is
detected as a ‘1’.
Therefore, a valid Start bit must satisfy both the above conditions to prevent the Noise Flag
from being set.
Data bits
The Noise Flag (NF) is set during normal data bit reception if the following condition occurs:
During the sampling of 16 samples, if all three samples numbered 8, 9 and10 are not the
same. The majority of the 8th, 9th and 10th samples is considered as the bit value.
Therefore, a valid Data bit must have samples 8, 9 and 10 at the same value to prevent the
Noise Flag from being set.
Figure 58.
Bit sampling in Reception mode
RDI line
Sample
clock
123456
78
9
10
11
12
13
14
15
16
sampled values
One bit time
6/16
7/16