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Obsolete
Product(s)
- Obsolete
Product(s)
On-chip peripherals
ST72324B-Auto
SPI Control/Status Register (SPICSR)
fCPU/16
0
1
fCPU/32
1
0
fCPU/64
0
1
0
fCPU/128
0
1
SPICSR
Reset value: 0000 0000 (00h)
7
654
32
10
SPIF
WCOL
OVR
MODF
Reserved
SOD
SSM
SSI
RO
-
R/W
Table 57.
SPICSR register description
Bit
Name
Function
7
SPIF
Serial Peripheral data transfer flag
This bit is set by hardware when a transfer has been completed. An interrupt is
generated if SPIE = 1 in the SPICR register. It is cleared by a software sequence (an
access to the SPICSR register followed by a write or a read to the SPIDR register).
0: Data transfer is in progress or the flag has been cleared
1: Data transfer between the device and an external device has been completed.
Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the
SPICSR register is read.
6WCOL
Write Collision status
This bit is set by hardware when a write to the SPIDR register is done during a
transmit sequence. It is cleared by a software sequence (see
Figure 53).
0: No write collision occurred
1: A write collision has been detected.
5OVR
SPI Overrun error
This bit is set by hardware when the byte currently being received in the shift register
is ready to be transferred into the SPIDR register while SPIF = 1 (see
Overrunregister. The OVR bit is cleared by software reading the SPICSR register.
0: No overrun error
1: Overrun error detected
4MODF
Mode Fault flag
This bit is set by hardware when the SS pin is pulled low in master mode (see
SPIE = 1 in the SPICSR register. This bit is cleared by a software sequence (An
access to the SPICR register while MODF = 1 followed by a write to the SPICR
register).
0: No master mode fault detected
1: A fault in master mode has been detected.
3
-
Reserved, must be kept cleared.
Table 56.
SPI master mode SCK frequency (continued)
Serial clock
SPR2
SPR1
SPR0