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Power saving modes
ST72324B-Auto
8.4
Active Halt and Halt modes
Active Halt and Halt modes are the two lowest power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruction. The decision to enter either in Active
Halt or Halt mode is given by the MCC/RTC interrupt enable flag (OIE bit in the MCCSR
register).
8.4.1
Active Halt mode
Active Halt mode is the lowest power consumption mode of the MCU with a real-time clock
available. It is entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock
The MCU can exit Active Halt mode on reception of either an MCC/RTC interrupt, a specific
means of an interrupt, no 256 or 4096 CPU cycle delay occurs. The CPU resumes operation
by servicing the interrupt or by fetching the reset vector which woke it up (see
Figure 25).When entering Active Halt mode, the I[1:0] bits in the CC register are forced to ‘10b’ to
enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
In Active Halt mode, only the main oscillator and its associated counter (MCC/RTC) are
running to keep a wake-up time base. All other peripherals are not clocked except those
which get their clock supply from another clock generator (such as external or auxiliary
oscillator).
The safeguard against staying locked in Active Halt mode is provided by the oscillator
interrupt.
Note:
As soon as the interrupt capability of one of the oscillators is selected (MCCSR.OIE bit set),
entering Active Halt mode while the Watchdog is active does not generate a reset.
This means that the device cannot spend more than a defined delay in this power saving
mode.
Caution:
When exiting Active Halt mode following an interrupt, OIE bit of MCCSR register must not be
cleared before tDELAY after the interrupt occurs (tDELAY = 256 or 4096 tCPU delay depending
on option byte). Otherwise, the ST7 enters Halt mode for the remaining tDELAY period.
Figure 24.
Active Halt timing overview
1.
This delay occurs only if the MCU exits Active Halt mode by means of a reset.
Table 26.
MCC/RTC low power mode selection
MCCSR OIE bit
Power saving mode entered when HALT instruction is executed
0
Halt mode
1
Active Halt mode
Halt
Run
256 or 4096 CPU
cycle delay(1)
Reset
or
interrupt
Halt
instruction
Fetch
vector
Active
[MCCSR.OIE = 1]