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| 型号： | ST72T85A5Q6 |
| 厂商： | 意法半导体 |
| 英文描述： | 8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES |
| 中文描述： | 8位微控制器48,000铁路发展策略光盘，3K内存，ADC，两个定时器，2个SPI，I2C和脊髓损伤接口 |
| 文件页数： | 35/117页 |
| 文件大小： | 748K |
| 代理商： | ST72T85A5Q6 |
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ST7285C
4.3 16-BIT TIMER
4.3.1 Introduction
One or more Timers may be present in the MCU,
depending on product specification. Please refer
to the Block Diagram to ascertain available prod-
uct resources, and to the Memory Map for register
addresses.
Each timer consists of a 16-bit free-running coun-
ter driven by a programmable prescaler, as well as
the control logic required to implement two input
capture and two output compare registers. The
timer may be used for a variety of purposes,
amongst which pulse length measurement of up to
two input signals and generation of up to two out-
put waveforms (e.g. PWM). The Timer Block Dia-
gram is illustrated in Figure 1.
Pulse lengths and waveform periods canvary from
a few microseconds to many seconds, thanks to
the programmable prescaler. When running with a
4MHz internal CPU clock, the timer can have a
resolution of 0.5, 1 or 2
μ
s, depending on the set-
ting of the clock control bits in the Timer Control
Register (TCR2). A software selectable external
clock input pin is available.
Since the timer has a 16-bit architecture, each of
its specific functional blocks is associated with a
register pair. These registers contain the high or-
der byte and the low order byte respectively of the
related function. Access to the high order byte in-
hibits the associated timer function until the low or-
der byte is also accessed.
Correct software procedures should set bit ‘I’ of
the Condition Code Register before accessing the
high order byte to prevent an interrupt from occur-
ring between accesses to the high and low order
bytes of any register.
In normal operating mode, reading the MSB of the
Input Capture register inhibits Input Capture until
the LSB is read. This mechanism allows Input cap-
ture to be disabled when the pin is connected to an
I/O bit.
When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) features are selected to-
gether, the PWM mode is the only active one.
4.3.2 Counter
The key element of the Programmable Timer is a
16-bit free running counter and its associated reg-
ister. The counter is preceeded by a prescaler
which divides the internal clock by two, four or
eight, depending on the setting of the clock control
bits of the Timer Control Register (TCR2), as illus-
trated in Table 1 below.
Table 7. Clock Control Bits
Software can read the counter at any time without
affecting its value, either from the Counter Regis-
ters or from the Alternate Counter Registers. The
only difference between these two read-only regis-
ter pairs is the way the overflow flag (TOF) is han-
dled during a read sequence.
A read sequence where only the least significant
byte of the free running counter is read (from either
the Counter Register or the Alternate Counter
Register), will receive the LSB of the count value
at the time of the read.
A read of the most significant byte (from either the
Counter Register or the Alternate Counter Regis-
ter) simultaneously returns the MSB of the count
value and causes the LSB to be transferred to a
buffer. The buffered value remains unchanged un-
til the 16-bit read sequence is completed, even if
the user reads the MSB several times. The read
sequence is completed by reading the LSB, which
actually returns the buffered value.
As shown in Figure 2, Figure 3 and Figure 4, the
free-running counter is set to FFFCh on Reset.
During a Power-On Reset (POR) cycle, the coun-
ter is loaded with FFFCh and begins running.
CC1
0
0
1
1
CC0
0
1
0
1
Clock Divisor
4
2
8
External Clock
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