- 您现在的位置：买卖IC网 > PDF目录385871 > ST72T85A5Q6 (意法半导体) 8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES PDF资料下载
参数资料
| 型号： | ST72T85A5Q6 |
| 厂商： | 意法半导体 |
| 英文描述： | 8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES |
| 中文描述： | 8位微控制器48,000铁路发展策略光盘，3K内存，ADC，两个定时器，2个SPI，I2C和脊髓损伤接口 |
| 文件页数： | 47/117页 |
| 文件大小： | 748K |
| 代理商： | ST72T85A5Q6 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页当前第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页
47/117
ST7285C
SERIAL PERIPHERAL INTERFACE
(Cont’d)
4.4.4 Signal Description
The four basic signals (MOSI, MISO, SCK andSS)
are described in the following paragraphs. Each
signal function is described for both the Master
and Slave mode.
The SPE (Serial Peripheral Enable) bit of the SPI
Control Register enables and disables the SPI (ac-
tive high); when the SPI is enabled the associated
alternate functions will be attributed to the relevant
I/O pins.
The SPI baud rate is the CPU clock divided by a
factor defined by software (2, 4, 16, 32).
4.4.5 Master Out Slave In (MOSI)
The MOSI pin is configured as a data output in the
Master (mode) device and as a data input in the
Slave (mode) device.
In this manner data is transferred serially from a
Master to a Slave on this line, most significant bit
first, least significant bit last. The timing diagrams
shown in the ELECTRICAL CHARACTERISTICS
section, CONTROL TIMING subsection, illustrate
SPI timing and show the relationship between data
and clock (SCK).
Four possible timing relationships may be chosen
by using control bits CPOL and CPHA. The Master
device always allows data to be applied on the
MOSI line a half-cycle before the clock edge
(SCK) to allow the Slave device to latch the data.
Both the Slave device(s) and a Master device
must be programmed to similar modes for proper
data transfer.
When the Master device transmits data to a sec-
ond (Slave) device via the MOSI line, the Slave
device responds by sending data to the Master de-
vice via the MISO line. This implies full duplex
transmission with both data out and data in syn-
chronized with the same clock signal (which is pro-
vided by the Master device). Thus, the byte trans-
mitted is replaced by the byte received and elimi-
nates the need for separate transmit-empty and
receiver-full status bits. A single status bit SPIF) is
used to signify that the I/O operation is complete.
Configuration of the MOSI pin is a function of the
MSTR bit in the Serial Peripheral Control Register
(SPCR). When operating as a Master, the user
should set the MSTR bit, defining the MOSI pin as
an output
4.4.6 Master In Slave Out (MISO)
The MISO pin is configured as an input in a Master
(mode) device and as an output in a Slave (mode)
device. In this manner data is transferred serially
from a Slave to a Master on this line, most signifi-
cant bit first,least significant bit last. The MISO pin
of a Slave device is placed in the high-impedance
state if it is not selected by the Master, i.e. itsSS
pin is at a logic high level. The timing diagram
shows the relationship between data and clock
(SCK). Four possible timing relationships may be
chosen by using control bits CPOL and CPHA. The
Master device always allows data to be applied on
the MOSI line a half-cycle before the clock edge
(SCK) in order for the Slave device to latch the da-
ta.
Note.
The Slave device and a Master device must
be programmed with similar timing modes for
proper data transfer.
When the Master device transmits data to a Slave
device via the MOSI line, the Slave device re-
sponds by sending data to Master device via the
MISO line. This implies full duplex transmission
with both data out and data in synchronized with
the same clock signal (one which is provided by
the Master device.) Thus, the byte transmitted is
replaced by the byte received and eliminates the
need for separate transmit-empty and receiver-full
bits. A single status bit (SPIF) in the Serial Periph-
eral Status Register (SPSR) is used to signify that
the I/O operation is complete.
In the Master device, the MSTR control bit in the
Serial Peripheral Control Register (SPCR) should
be set (by the program) to allow the Master device
to receive data on its MISO pin. In the Slave de-
vice, its MISO pin is enabled by the logic high level
present on theSS pin: i.e. ifSS = 1 the MISO pin is
placed in the high-impedance state, whereas ifSS
= 0 the MISO pin is an output for the Slave device.
相关PDF资料 |
PDF描述 |
|---|---|
| ST730C08L3 | PHASE CONTROL THYRISTORS |
| ST730C08L3L | PHASE CONTROL THYRISTORS |
| ST730C12L0 | PHASE CONTROL THYRISTORS |
| ST730C12L0L | PHASE CONTROL THYRISTORS |
| ST730C12L1 | PHASE CONTROL THYRISTORS |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ST730 | 制造商:IRF 制造商全称:International Rectifier 功能描述:PHASE CONTROL THYRISTORS Hockey Puk Version |
| ST7-30 | 制造商:SUPERWORLD 制造商全称:Superworld Electronics 功能描述:POWER TRANSFORMER |
| ST-7300 | 制造商:GC Electronics 功能描述: |
| ST730186-3 | 制造商:KEMET Corporation 功能描述: 制造商:KET 功能描述: |
| ST730268-1 | 制造商:KEMET Corporation 功能描述: 制造商:KET 功能描述: |
发布紧急采购，3分钟左右您将得到回复。