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参数资料
| 型号： | ST72T85A5Q6 |
| 厂商： | 意法半导体 |
| 英文描述： | 8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES |
| 中文描述： | 8位微控制器48,000铁路发展策略光盘，3K内存，ADC，两个定时器，2个SPI，I2C和脊髓损伤接口 |
| 文件页数： | 59/117页 |
| 文件大小： | 748K |
| 代理商： | ST72T85A5Q6 |
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ST7285C
I
2
C BUS INTERFACE
(Cont’d)
CONTROL REGISTER (CR)
Address: 0028h
Reset Value: 00h
—
Read / Write
b7-6 = reserved.
b5:
PE
Peripheral Enable
1 : Master/Slave capability.
0 : Peripheral disabled ( all outputs are released).
When this bit is reset, all the bits of the control reg-
ister and the status register except the Stop bit are
reset.
PE selects the alternate function on the corre-
sponding I/O.
This bit is set by software and it is cleared by soft-
ware or by a reset.
b4:
ENGC
Enable General call
When this bit is set, the peripheral acknowledges
the general call address.
Engc bit is set or cleared by software. It is cleared
when the peripheral is disabled (PE=0) or by reset.
b3:
START
Generation of a Start condition
When the Start bit is set in Slave mode, the inter-
face generates a Start condition as soon as the
bus is free. In Master mode, it generates a repeat-
ed Startcondition. Then an interrupt is generated if
ITE is set.
This bit is set by software and is cleared by soft-
ware, when the peripheral is disabled (PE=0) or by
reset. It is automatically cleared after the start con-
dition is sent.
b2:
ACK
Acknowledge level
When this bit is set, an acknowledge is returned
after an address byte is received or after a data
byte is received.
When it is cleared, no acknowledge is returned.
It is set by software and it is cleared by software,
when the peripheral is disabled (PE=0) or byreset.
b1:
STOP
Generation of a Stop condition
If the Stop bit is set in Master mode then a stop
condition is generated after the transfer of the cur-
rent byte or after that the current Start condition is
sent.
If it is set in Slave mode then both SCL and SDA
lines are released in order to recover from an error
condition and the peripheral waits for a detection
of a Start or a Stop condition. Then the interface
waits for a Stop or a Start condition on the lines.
This bit can be cleared by software. It is automati-
cally cleared after the stop condition is sent on the
SCL line in Master mode or by reset.
b0:
ITE
Interrupt Enable
When the Interrupt Enable bit is set, the I
2
C inter-
face interrupt is generated after anyone of these
following conditions
– A Start condition is generated in Master mode.
– The address is matched in Slave mode while the
ACK flag is at a logic high.
– A data byte has been received or is to be trans-
mitted.
– A loss of arbitration of the bus to another Master
in Master mode.
– A misplaced Start or Stop condition is detected
– There is no acknowledge.
– A Stop condition has been detected in Slave
mode. While the ITE flag is set, an interrupt is
generated, SCL is hold low and the transfer is
suspended except when a loss of arbitration or a
detection of a Stop condition have been detect-
ed. ITEis reset by software, when the peripheral
is disabled (PE=0) or by reset.
7
0
-
-
PE
ENGC
START
ACK
STOP
ITE
PE = 0
PA6 = normal I/O
PA4 = normal I/O
PE = 1
PA6 = I
2
C DATA
PA4 = I
2
C CLOCK
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