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参数资料
型号： ST72T85A5Q6
厂商： 意法半导体
英文描述： 8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES
中文描述： 8位微控制器48,000铁路发展策略光盘，3K内存，ADC，两个定时器，2个SPI，I2C和脊髓损伤接口
文件页数： 67/117页
文件大小： 748K
代理商： ST72T85A5Q6
67/117
ST7285C
RDS FILTER (
Cont’d)
4.7.2 Functional Description
The RDS filter is of classical Switched Capacitor
type, comprising: an anti-aliasing filter, the SC-fil-
ter proper and a smoothing filter connected in cas-
cade. The block diagram is given inFigure 33.
The Filter peripheral is composed of the following
functional blocks:
–
Prefilter
. The anti-aliasing filter consists of a 2
nd
order Sallen-Key filter. The phase response in
the passband is linear. The cut-off frequency is
located at about 360KHz. The prefilter includes
an operational amplifier with a gain of 80 dB.
–
SC Filter
. The SC filter is a 8
th
order bandpass
filter. It comprises 4 cascaded biquads. The bi-
quads all have the same scheme and differ only
in their capacitor values. The switches are con-
trolled by a clock generator which produces non-
overlapping clock phases.
–
Buffer
. The output of the SC-Filter cannot be
connected to resistive loads, since this would se-
verely reduce its gain. A buffer is therefore con-
nected between the SC filter and the smoothing
filter.
–
Smoothing filter
. The smoothing filter connect-
ed to the Sc-filter (through the Buffer) is a simple
RC low pass filter. The output is connected to
RDSFIL pin (external connection) and to the
Comparator.
–
Comparator
. The comparator is connected to
the smoothing filter and is able to detect zero-
crossing in less than 125ns. The digital output of
the comparator is connected via a port to the
RDS demodulator.
–
D/A Converter
. A maximum offset of 1mV is al-
lowed on the comparator’s inputs. The offset
compensation is achieved as follows:
in a software selectable test mode, the input of
the filter is switched to RDSREF (=2.5V). The D/
A converter register (RDSFi1) is set to zero and
then incremented by software until the compara-
tor changes its sign.
–
Test Mode Selector
. This function is controlled
via 4 bits in the filter control register (RDS Fi2). It
selects the various test modes. (see next point).
– ST7 interface registers.
These are described
below.
RDS Fi1
Address 005Ah:
—
Read/Write Register
b7 = reserved.
b6 =
COMP
Comparator output (read only).
b5-0 =
AD5-AD0
Offset
correction
(1LSB=2mV).
value
output
by
D/A
RDS Fi2
Address 005Bh
—
Read/Write Register
b7-5 = reserved.
b4 =
PDB
Power down bit (1 = Run; 0 = Power-down)
b3-0 =
TM3-TM0
Mode select. Only Modes shown in the table below
are valid; other modes are reserved.
When the internal filter is switched off, the RDS-
COMP pin can be used as an input and to feed the
demodulator from an external filter.
7
6
5
4
3
2
1
0
-
COMP
AD5
AD4
AD3
AD2
AD1
AD0
7
6
5
4
3
2
1
0
-
-
-
PDB
TM3
TM2
TM1
TM0
TM3
0
0
TM2
0
0
TM1
0
1
TM0
0
1
Mode
filter off (reset state)
normal operating mode
offset compensation
mode
1
1
0
1
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